1. 03 2月, 2015 1 次提交
  2. 31 1月, 2015 1 次提交
    • T
      clk: ti: add omap3 legacy clock data · 74807dff
      Tero Kristo 提交于
      Introduces omap3 legacy clock data under clock driver. The clock data
      is also in new format, which makes it possible to get rid of the
      clk-private.h header. This patch also introduces SoC specific init
      functions that shall be called from the low level init.
      
      The data format used in this file has two possible evolution paths;
      it can either be removed completely once no longer needed, or it will
      be possible to retain the format and modify the TI clock driver to be
      a loadable module at some point. The actual path to be followed
      will be decided later.
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Signed-off-by: NMichael Turquette <mturquette@linaro.org>
      74807dff
  3. 28 1月, 2015 1 次提交
  4. 16 12月, 2014 1 次提交
  5. 14 11月, 2014 3 次提交
  6. 29 9月, 2014 1 次提交
    • T
      clk: ti: change clock init to use generic of_clk_init · c08ee14c
      Tero Kristo 提交于
      Previously, the TI clock driver initialized all the clocks hierarchically
      under each separate clock provider node. Now, each clock that requires
      IO access will instead check their parent node to find out which IO range
      to use.
      
      This patch allows the TI clock driver to use a few new features provided
      by the generic of_clk_init, and also allows registration of clock nodes
      outside the clock hierarchy (for example, any external clocks.)
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Cc: Mike Turquette <mturquette@linaro.org>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
      Cc: Jyri Sarha <jsarha@ti.com>
      Cc: Stefan Assmann <sassmann@kpanic.de>
      Acked-by: NTony Lindgren <tony@atomide.com>
      c08ee14c
  7. 07 6月, 2014 1 次提交
    • A
      ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) · ce369a54
      Andrii Tseglytskyi 提交于
      Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at
      frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x.
      
      MPU DPLL has a limitation on the maximum frequency it can be locked
      at. Duty Cycle Correction circuit is used to recover a correct duty
      cycle for achieving higher frequencies (hardware internally switches
      output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)).
      
      For further information, See the note on OMAP5432 Technical Reference
      Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters",
      and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5"
      chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is
      present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P).
      Signed-off-by: NAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>
      Signed-off-by: NTaras Kondratiuk <taras@ti.com>
      Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
      Signed-off-by: NNishanth Menon <nm@ti.com>
      [t-kristo@ti.com: added TRM / DM references for DCC clock rate]
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      ce369a54
  8. 28 5月, 2014 5 次提交
  9. 20 2月, 2014 1 次提交
  10. 18 1月, 2014 16 次提交