提交 8425dbaa 编写于 作者: J John Davis

OcCpuLib: Fixed crash while using SysReport on Pentium 4 systems

MSRs MSR_IA32_EXT_CONFIG and MSR_CORE_FSB_FREQ are not supported on P4 platforms, limiting to Yonah and newer only
上级 937d76b1
...@@ -7,6 +7,7 @@ OpenCore Changelog ...@@ -7,6 +7,7 @@ OpenCore Changelog
- Updated builtin zlib library to 1.2.12 - Updated builtin zlib library to 1.2.12
- Changed ocpasswordgen not to print characters on password input - Changed ocpasswordgen not to print characters on password input
- Added ProcessKernel utility for testing kext injection based on configs - Added ProcessKernel utility for testing kext injection based on configs
- Fixed crash while using `SysReport` on Pentium 4 systems
#### v0.8.3 #### v0.8.3
- Added ext4 file system driver - Added ext4 file system driver
......
...@@ -35,7 +35,8 @@ ...@@ -35,7 +35,8 @@
typedef enum { typedef enum {
OcCpuGenerationUnknown, OcCpuGenerationUnknown,
OcCpuGenerationBanias, OcCpuGenerationBanias,
OcCpuGenerationPrePenryn, OcCpuGenerationPreYonah,
OcCpuGenerationYonahMerom,
OcCpuGenerationPenryn, OcCpuGenerationPenryn,
OcCpuGenerationNehalem, OcCpuGenerationNehalem,
OcCpuGenerationBonnell, OcCpuGenerationBonnell,
......
...@@ -56,7 +56,6 @@ ...@@ -56,7 +56,6 @@
#define MSR_IA32_PERF_CONTROL 0x199 #define MSR_IA32_PERF_CONTROL 0x199
#define MSR_THERM2_CTL 0x19D #define MSR_THERM2_CTL 0x19D
#define MSR_IA32_MISC_ENABLES 0x1A0
#define TURBO_DISABLE_MASK ((UINT64)1 << 38) #define TURBO_DISABLE_MASK ((UINT64)1 << 38)
#define TURBO_MODE_DISABLE_BIT 38 #define TURBO_MODE_DISABLE_BIT 38
......
...@@ -551,7 +551,8 @@ ScanIntelProcessor ( ...@@ -551,7 +551,8 @@ ScanIntelProcessor (
// If we are under virtualization, then we should get the topology from CPUID the same was as with Penryn. // If we are under virtualization, then we should get the topology from CPUID the same was as with Penryn.
// //
if ( (Cpu->MaxId >= CPUID_CACHE_PARAMS) if ( (Cpu->MaxId >= CPUID_CACHE_PARAMS)
&& ( (Cpu->CpuGeneration == OcCpuGenerationPrePenryn) && ( (Cpu->CpuGeneration == OcCpuGenerationPreYonah)
|| (Cpu->CpuGeneration == OcCpuGenerationYonahMerom)
|| (Cpu->CpuGeneration == OcCpuGenerationPenryn) || (Cpu->CpuGeneration == OcCpuGenerationPenryn)
|| (Cpu->CpuGeneration == OcCpuGenerationBonnell) || (Cpu->CpuGeneration == OcCpuGenerationBonnell)
|| (Cpu->CpuGeneration == OcCpuGenerationSilvermont) || (Cpu->CpuGeneration == OcCpuGenerationSilvermont)
...@@ -584,7 +585,7 @@ ScanIntelProcessor ( ...@@ -584,7 +585,7 @@ ScanIntelProcessor (
// //
Cpu->CoreCount = 0; Cpu->CoreCount = 0;
Cpu->ThreadCount = 0; Cpu->ThreadCount = 0;
} else if ( (Cpu->CpuGeneration == OcCpuGenerationPrePenryn) } else if ( (Cpu->CpuGeneration == OcCpuGenerationPreYonah)
&& (Cpu->MaxId < CPUID_CACHE_PARAMS)) && (Cpu->MaxId < CPUID_CACHE_PARAMS))
{ {
// //
...@@ -1024,24 +1025,26 @@ OcCpuGetMsrReport ( ...@@ -1024,24 +1025,26 @@ OcCpuGetMsrReport (
Report->CpuHasMsrE2 = TRUE; Report->CpuHasMsrE2 = TRUE;
Report->CpuMsrE2Value = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL); Report->CpuMsrE2Value = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
} }
} else if (CpuInfo->CpuGeneration >= OcCpuGenerationPrePenryn) { } else if (CpuInfo->CpuGeneration >= OcCpuGenerationPreYonah) {
// if (CpuInfo->CpuGeneration >= OcCpuGenerationYonahMerom) {
// MSR_IA32_MISC_ENABLE //
// // MSR_IA32_EXT_CONFIG
Report->CpuHasMsrIa32MiscEnable = TRUE; //
Report->CpuMsrIa32MiscEnableValue = AsmReadMsr64 (MSR_IA32_MISC_ENABLES); Report->CpuHasMsrIa32ExtConfig = TRUE;
Report->CpuMsrIa32ExtConfigValue = AsmReadMsr64 (MSR_IA32_EXT_CONFIG);
// //
// MSR_IA32_EXT_CONFIG // MSR_CORE_FSB_FREQ
// //
Report->CpuHasMsrIa32ExtConfig = TRUE; Report->CpuHasMsrFsbFreq = TRUE;
Report->CpuMsrIa32ExtConfigValue = AsmReadMsr64 (MSR_IA32_EXT_CONFIG); Report->CpuMsrFsbFreqValue = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
}
// //
// MSR_CORE_FSB_FREQ // MSR_IA32_MISC_ENABLE
// //
Report->CpuHasMsrFsbFreq = TRUE; Report->CpuHasMsrIa32MiscEnable = TRUE;
Report->CpuMsrFsbFreqValue = AsmReadMsr64 (MSR_CORE_FSB_FREQ); Report->CpuMsrIa32MiscEnableValue = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
// //
// MSR_IA32_PERF_STATUS // MSR_IA32_PERF_STATUS
...@@ -1331,6 +1334,10 @@ InternalDetectIntelProcessorGeneration ( ...@@ -1331,6 +1334,10 @@ InternalDetectIntelProcessorGeneration (
case CPU_MODEL_DOTHAN: case CPU_MODEL_DOTHAN:
CpuGeneration = OcCpuGenerationBanias; CpuGeneration = OcCpuGenerationBanias;
break; break;
case CPU_MODEL_YONAH:
case CPU_MODEL_MEROM:
CpuGeneration = OcCpuGenerationYonahMerom;
break;
case CPU_MODEL_PENRYN: case CPU_MODEL_PENRYN:
CpuGeneration = OcCpuGenerationPenryn; CpuGeneration = OcCpuGenerationPenryn;
break; break;
...@@ -1414,13 +1421,13 @@ InternalDetectIntelProcessorGeneration ( ...@@ -1414,13 +1421,13 @@ InternalDetectIntelProcessorGeneration (
break; break;
default: default:
if (CpuInfo->Model < CPU_MODEL_PENRYN) { if (CpuInfo->Model < CPU_MODEL_PENRYN) {
CpuGeneration = OcCpuGenerationPrePenryn; CpuGeneration = OcCpuGenerationPreYonah;
} else if (CpuInfo->Model >= CPU_MODEL_SANDYBRIDGE) { } else if (CpuInfo->Model >= CPU_MODEL_SANDYBRIDGE) {
CpuGeneration = OcCpuGenerationPostSandyBridge; CpuGeneration = OcCpuGenerationPostSandyBridge;
} }
} }
} else { } else {
CpuGeneration = OcCpuGenerationPrePenryn; CpuGeneration = OcCpuGenerationPreYonah;
} }
DEBUG (( DEBUG ((
......
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