From 8425dbaa926b71089da739cb45d5fca80e1094e5 Mon Sep 17 00:00:00 2001
From: John Davis <goldfishnet@aol.com>
Date: Wed, 24 Aug 2022 21:14:03 -0500
Subject: [PATCH] OcCpuLib: Fixed crash while using SysReport on Pentium 4
 systems

MSRs MSR_IA32_EXT_CONFIG and MSR_CORE_FSB_FREQ are not supported on P4 platforms, limiting to Yonah and newer only
---
 Changelog.md                                  |  1 +
 Include/Acidanthera/Library/OcCpuLib.h        |  3 +-
 .../Intel/IndustryStandard/ProcessorInfo.h    |  1 -
 Library/OcCpuLib/OcCpuLib.c                   | 43 +++++++++++--------
 4 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/Changelog.md b/Changelog.md
index 470ded91..1c908fc4 100644
--- a/Changelog.md
+++ b/Changelog.md
@@ -7,6 +7,7 @@ OpenCore Changelog
 - Updated builtin zlib library to 1.2.12
 - Changed ocpasswordgen not to print characters on password input
 - Added ProcessKernel utility for testing kext injection based on configs
+- Fixed crash while using `SysReport` on Pentium 4 systems
 
 #### v0.8.3
 - Added ext4 file system driver
diff --git a/Include/Acidanthera/Library/OcCpuLib.h b/Include/Acidanthera/Library/OcCpuLib.h
index e7600b7a..1cc29403 100644
--- a/Include/Acidanthera/Library/OcCpuLib.h
+++ b/Include/Acidanthera/Library/OcCpuLib.h
@@ -35,7 +35,8 @@
 typedef enum {
   OcCpuGenerationUnknown,
   OcCpuGenerationBanias,
-  OcCpuGenerationPrePenryn,
+  OcCpuGenerationPreYonah,
+  OcCpuGenerationYonahMerom,
   OcCpuGenerationPenryn,
   OcCpuGenerationNehalem,
   OcCpuGenerationBonnell,
diff --git a/Include/Intel/IndustryStandard/ProcessorInfo.h b/Include/Intel/IndustryStandard/ProcessorInfo.h
index e95798b5..dab9eec0 100644
--- a/Include/Intel/IndustryStandard/ProcessorInfo.h
+++ b/Include/Intel/IndustryStandard/ProcessorInfo.h
@@ -56,7 +56,6 @@
 #define MSR_IA32_PERF_CONTROL    0x199
 #define MSR_THERM2_CTL           0x19D
 
-#define MSR_IA32_MISC_ENABLES   0x1A0
 #define TURBO_DISABLE_MASK      ((UINT64)1 << 38)
 #define TURBO_MODE_DISABLE_BIT  38
 
diff --git a/Library/OcCpuLib/OcCpuLib.c b/Library/OcCpuLib/OcCpuLib.c
index 0247708f..88db28ac 100644
--- a/Library/OcCpuLib/OcCpuLib.c
+++ b/Library/OcCpuLib/OcCpuLib.c
@@ -551,7 +551,8 @@ ScanIntelProcessor (
   // If we are under virtualization, then we should get the topology from CPUID the same was as with Penryn.
   //
   if (  (Cpu->MaxId >= CPUID_CACHE_PARAMS)
-     && (  (Cpu->CpuGeneration == OcCpuGenerationPrePenryn)
+     && (  (Cpu->CpuGeneration == OcCpuGenerationPreYonah)
+        || (Cpu->CpuGeneration == OcCpuGenerationYonahMerom)
         || (Cpu->CpuGeneration == OcCpuGenerationPenryn)
         || (Cpu->CpuGeneration == OcCpuGenerationBonnell)
         || (Cpu->CpuGeneration == OcCpuGenerationSilvermont)
@@ -584,7 +585,7 @@ ScanIntelProcessor (
     //
     Cpu->CoreCount   = 0;
     Cpu->ThreadCount = 0;
-  } else if (  (Cpu->CpuGeneration == OcCpuGenerationPrePenryn)
+  } else if (  (Cpu->CpuGeneration == OcCpuGenerationPreYonah)
             && (Cpu->MaxId < CPUID_CACHE_PARAMS))
   {
     //
@@ -1024,24 +1025,26 @@ OcCpuGetMsrReport (
       Report->CpuHasMsrE2   = TRUE;
       Report->CpuMsrE2Value = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
     }
-  } else if (CpuInfo->CpuGeneration >= OcCpuGenerationPrePenryn) {
-    //
-    // MSR_IA32_MISC_ENABLE
-    //
-    Report->CpuHasMsrIa32MiscEnable   = TRUE;
-    Report->CpuMsrIa32MiscEnableValue = AsmReadMsr64 (MSR_IA32_MISC_ENABLES);
+  } else if (CpuInfo->CpuGeneration >= OcCpuGenerationPreYonah) {
+    if (CpuInfo->CpuGeneration >= OcCpuGenerationYonahMerom) {
+      //
+      // MSR_IA32_EXT_CONFIG
+      //
+      Report->CpuHasMsrIa32ExtConfig   = TRUE;
+      Report->CpuMsrIa32ExtConfigValue = AsmReadMsr64 (MSR_IA32_EXT_CONFIG);
 
-    //
-    // MSR_IA32_EXT_CONFIG
-    //
-    Report->CpuHasMsrIa32ExtConfig   = TRUE;
-    Report->CpuMsrIa32ExtConfigValue = AsmReadMsr64 (MSR_IA32_EXT_CONFIG);
+      //
+      // MSR_CORE_FSB_FREQ
+      //
+      Report->CpuHasMsrFsbFreq   = TRUE;
+      Report->CpuMsrFsbFreqValue = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
+    }
 
     //
-    // MSR_CORE_FSB_FREQ
+    // MSR_IA32_MISC_ENABLE
     //
-    Report->CpuHasMsrFsbFreq   = TRUE;
-    Report->CpuMsrFsbFreqValue = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
+    Report->CpuHasMsrIa32MiscEnable   = TRUE;
+    Report->CpuMsrIa32MiscEnableValue = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
 
     //
     // MSR_IA32_PERF_STATUS
@@ -1331,6 +1334,10 @@ InternalDetectIntelProcessorGeneration (
       case CPU_MODEL_DOTHAN:
         CpuGeneration = OcCpuGenerationBanias;
         break;
+      case CPU_MODEL_YONAH:
+      case CPU_MODEL_MEROM:
+        CpuGeneration = OcCpuGenerationYonahMerom;
+        break;
       case CPU_MODEL_PENRYN:
         CpuGeneration = OcCpuGenerationPenryn;
         break;
@@ -1414,13 +1421,13 @@ InternalDetectIntelProcessorGeneration (
         break;
       default:
         if (CpuInfo->Model < CPU_MODEL_PENRYN) {
-          CpuGeneration = OcCpuGenerationPrePenryn;
+          CpuGeneration = OcCpuGenerationPreYonah;
         } else if (CpuInfo->Model >= CPU_MODEL_SANDYBRIDGE) {
           CpuGeneration = OcCpuGenerationPostSandyBridge;
         }
     }
   } else {
-    CpuGeneration = OcCpuGenerationPrePenryn;
+    CpuGeneration = OcCpuGenerationPreYonah;
   }
 
   DEBUG ((
-- 
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