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  1. 05 2月, 2021 1 次提交
  3. 03 2月, 2021 1 次提交
  5. 26 11月, 2019 1 次提交
  7. 13 10月, 2018 2 次提交
  9. 19 9月, 2018 1 次提交
    • B
      rcu: Make expedited GPs handle CPU 0 being offline · dfeb52bf
      由 Boqun Feng 提交于 
      Currently, the parallelized initialization of expedited grace periods uses
the workqueue associated with each rcu_node structure's ->grplo field.
This works fine unless that CPU is offline.  This commit therefore uses
the CPU corresponding to the lowest-numbered online CPU, or just queues
the work on WORK_CPU_UNBOUND if there are no online CPUs corresponding
to this rcu_node structure.

Note that this patch uses cpu_is_offline() instead of the usual approach
of checking bits in the rcu_node structure's ->qsmaskinitnext field.  This
is safe because preemption is disabled across both the cpu_is_offline()
check and the call to queue_work_on().
Signed-off-by: NBoqun Feng <boqun.feng@gmail.com>
[ paulmck: Disable preemption to close offline race window. ]
Signed-off-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
[ paulmck: Apply Peter Zijlstra feedback on CPU selection. ]
Tested-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      dfeb52bf
  11. 28 8月, 2018 4 次提交
    • P
      RISC-V: Fix sys_riscv_flush_icache · 9f6192e5
      由 Palmer Dabbelt 提交于 
      This contains a pair of patches that together fix sys_riscv_flush_icache
on all systems:

* The first enables sys_riscv_flush_icache() for non-SMP systems.
* The second fixes a bug in our syscall header that caused
  sys_riscv_flush_icache to never get generated.
      9f6192e5
    • P
      RISC-V: Don't use a global include guard for uapi/asm/syscalls.h · 73d15ed8
      由 Palmer Dabbelt 提交于 
      This file is expected to be included multiple times in the same file in
order to allow the __SYSCALL macro to generate system call tables.  With
a global include guard we end up missing __NR_riscv_flush_icache in the
syscall table, which results in icache flushes that escape the vDSO call
to not actually do anything.

The fix is to move to per-#define include guards, which allows the
system call tables to actually be populated.  Thanks to Macrus Comstedt
for finding and fixing the bug!

Cc: Marcus Comstedt <marcus@mc.pp.se>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      73d15ed8
    • P
      RISC-V: Define sys_riscv_flush_icache when SMP=n · eb1cb15e
      由 Palmer Dabbelt 提交于 
      This would be necessary to make non-SMP builds work, but there is
another error in the implementation of our syscall linkage that actually
just causes sys_riscv_flush_icache to never build.  I've build tested
this on allnoconfig and allnoconfig+SMP=y, as well as defconfig like
normal.

CC: Christoph Hellwig <hch@infradead.org>
CC: Guenter Roeck <linux@roeck-us.net>
In-Reply-To: <20180809055830.GA17533@infradead.org>
In-Reply-To: <20180809132612.GA31058@roeck-us.net>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      eb1cb15e
    • D
      riscv: Delete asm/compat.h · 7bc738f1
      由 Deepa Dinamani 提交于 
      riscv does not enable CONFIG_COMPAT in default configurations:
defconfig, allmodconfig and allnoconfig.
Remove the asm/compat.h as it does not seem to add any value to
the architecture without CONFIG_COMPAT.

Now that time compat syscalls are being reused in non CONFIG_COMPAT
modes, asm-generic/compat.h provides definitions for riscv 32 bit
mode.
Reviewed-by: NChristoph Hellwig <hch@lst.de>
Signed-off-by: NDeepa Dinamani <deepa.kernel@gmail.com>
Cc: palmer@sifive.com
Cc: linux-riscv@lists.infradead.org
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      7bc738f1
  13. 23 8月, 2018 3 次提交
  15. 22 8月, 2018 1 次提交
  17. 21 8月, 2018 7 次提交
    • Z
      riscv: clean up config · 967b33cd
      由 Zihao Yu 提交于
      967b33cd
    • Z
      riscv: fix issue of no DMA buffer for eth · cdbec504
      由 Zihao Yu 提交于 
      * By default, dev.coherent_dma_mask is DMA_BIT_MASK(32) for all devices.
  But when we put the kernel over 4GB physical memory, devices can not
  get DMA buffer with this default mask. Setting this mask to
  DMA_BIT_MASK(64) can fix this issue. Note that by default
  arch_setup_pdev_archdata() is defined as a weak function.
      cdbec504
    • Z
      riscv: fix "Cannot allocate SWIOTLB buffer" · 63eef6e8
      由 Zihao Yu 提交于 
      * By default, ARCH_LOW_ADDRESS_LIMIT is 0xffff_ffffUL. When we put the
  kernel over 4GB physical memory, swiotlb can not get free memory below
  ARCH_LOW_ADDRESS_LIMIT. Modifying ARCH_LOW_ADDRESS_LIMIT to
  0xf_ffff_ffffUL can fix this issue.
      63eef6e8
    • Z
      riscv: add dummy eth · 94dfd6b6
      由 Zihao Yu 提交于 
      * it compiles, but cannot allocate dma buffer at runtime
      94dfd6b6
    • C
      PCI/xilinx: Depend on OF instead of the ARCH · 76103a26
      由 Christoph Hellwig 提交于 
      There isn't a hard dependency of the Xilinx AXI-PCIe host bridge on any
architecture.  For example: at SiFive we map RISC-V cores to Xilinx FPGAs
and connect the Xilinx IP via a TileLink adapter, so the RISC-V Linux
port will need to be able to enable PCIE_XILINX in order to have PCIe
support.

This patch decouples the PCIE_XILINX support from ARCH.  Instead it just
depends on OF, which is the only true dependency.
Signed-off-by: NPalmer Dabbelt <palmer@dabbelt.com>
[hch: switch to OF instead of OF_PCI now that the latter is gone]
Signed-off-by: NChristoph Hellwig <hch@lst.de>
[lorenzo.pieralisi@arm.com: trimmed the commit log]
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      76103a26
    • W
      base: fix order of OF initialization · 5ca42fb9
      由 Wesley W. Terpstra 提交于 
      This fixes: [    0.010000] cpu cpu0: Error -2 creating of_node link
... which you get for every CPU on all architectures that use
CONFIG_GENERIC_CPU_DEVICES.

In that case, driver_init() calls cpu_dev_init() before calling
of_core_init(). Then we get the callchain:

  cpu_dev_init()
    -> cpu_dev_register_generic()
    -> register_cpu(cpu, i)
    -> device_register(&cpu->dev)
    -> device_add(dev)
    -> device_add_class_symlinks(dev)

... in device_add_class_symlinks, we we dev->of_node, and call
sysfs_create_link(), which fails because we haven't called
of_core_init() to register the sysfs devicetree directory yet.
Signed-off-by: NWesley W. Terpstra <wesley@sifive.com>
[hch: updated the changelog based on review feedback]
Signed-off-by: NChristoph Hellwig <hch@lst.de>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NFrank Rowand <frowand.list@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      5ca42fb9
    • P
      RISC-V Updates for the 4.19 Merge Window · 33e7d009
      由 Palmer Dabbelt 提交于 
      This tag contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make it
to userspace.  Support for three devices has been added:

* Support for the ISA-mandated timers on RISC-V systems.
* Support for the ISA-mandated first-level interrupt controller on
  RISC-V systems, which is handled as part of our core arch code because
  it's very small and tightly tied to the ISA.
* Support for SiFive's platform-level interrupt controller, which talks
  to the actual devices.

In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:

* Build fixes for various configurations
    * A fix to the vDSO build's makefile so it respects CFLAGS.
    * The addition of __lshrti3, a libgcc derived function necessary for
      some 32-bit configurations.
    * !SMP && PERF_EVENTS
* Cleanups to the arch code to remove the remnants of old versions of
  the drivers that were just properly submitted.
    * Some dead code from the timer driver, most of which wasn't ever
      even compiled.
    * Cleanups of some interrupt #defines, which are now local to the
      interrupt handling code.
* Fixes to ptrace(), which while not being sufficient to fully make GDB
  work are at least sufficient to get simple GDB tasks to work.
* Early printk support via RISC-V's architecturally mandated SBI console
  device.
* A fix to our early debug trap handler to ensure it's always aligned.

These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches.  The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.

This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
the HiFive Unleashed.

Thanks to Christoph Hellwig and the other guys at WD for getting the new
drivers in shape!
      33e7d009
  19. 14 8月, 2018 2 次提交
  21. 13 8月, 2018 17 次提交