Merge pull request #1 from LvNA-system/add-dummy-eth

Add dummy eth

arch/riscv/Kconfig

@@ -222,6 +222,8 @@ endmenu
 
 menu "Bus support"
 
+source "arch/riscv/drivers/Kconfig"
+
 config PCI
 	bool "PCI support"
 	select PCI_MSI

arch/riscv/Makefile

@@ -80,4 +80,6 @@ core-y += arch/riscv/kernel/ arch/riscv/mm/
 
 libs-y += arch/riscv/lib/
 
+drivers-y += arch/riscv/drivers/
+
 all: vmlinux

arch/riscv/drivers/Kconfig

+config ETH_XILINX_RV
+	bool "Xilinx AXI dummy eth support for RV"
+	depends on RISCV
+	help
+  Say 'Y' here if you want kernel to support the Xilinx AXI dummy eth driver.

arch/riscv/drivers/Makefile

+obj-$(CONFIG_ETH_XILINX_RV) += xilinx_dummy_eth_main.o

arch/riscv/include/asm/processor.h

@@ -92,6 +92,8 @@ extern int riscv_of_processor_hart(struct device_node *node);
 
 extern void riscv_fill_hwcap(void);
 
+#define ARCH_LOW_ADDRESS_LIMIT  (0xfffffffffUL)
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_PROCESSOR_H */

arch/riscv/mm/Makefile

@@ -3,3 +3,4 @@ obj-y += fault.o
 obj-y += extable.o
 obj-y += ioremap.o
 obj-y += cacheflush.o
+obj-y += dma.o

arch/riscv/mm/dma.c

+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+void arch_setup_pdev_archdata(struct platform_device *pdev)
+{
+	if (pdev->dev.coherent_dma_mask == DMA_MASK_NONE &&
+	    pdev->dev.dma_mask == NULL) {
+		pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+		pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+	}
+}