Merge branch 'southlake' of github.com:OpenXiangShan/nexus-am into southlake

am/src/nemu/include/nemu.h

@@ -26,7 +26,7 @@
 # define SYNC_ADDR    0x40001004
 # define FB_ADDR      0x50000000
 #elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
-# define RTC_ADDR     0x1f0000bff8
+# define RTC_ADDR     0x1f1000bff8
 // CLINT 0x1f00000000
 #else
 # define SERIAL_PORT  0xa10003f8

am/src/nemu/isa/riscv/vme.c

@@ -21,7 +21,7 @@ static const _Area segments[] = {      // Kernel memory mappings
   RANGE_LEN(0xc0000000, 0x100000),  // page table test allocates from this position
 #elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
   RANGE_LEN(0x2000000000, 0x8000000), // PMEM
-  RANGE_LEN(0x1f10050000, 0x1000),    // uart
+  RANGE_LEN(0x1f00050000, 0x1000),    // uart
   // RANGE_LEN(CLINT_MMIO, 0x10000),     // clint/timer
   // RANGE_LEN(0x1f0c000000, 0x4000000), // PLIC
   RANGE_LEN(0x2040000000, 0x100000),  // page table test allocates from this position

am/src/southlake/common/uartlite.c

@@ -3,7 +3,7 @@
 #include <riscv.h>
 #include <klib.h>
 
-#define UARTLITE_MMIO 0x1f10050000
+#define UARTLITE_MMIO 0x1f00050000
 #define UARTLITE_RX_FIFO  0x0
 #define UARTLITE_TX_FIFO  0x4
 #define UARTLITE_STAT_REG 0x8

am/src/xs/include/xs.h

@@ -13,10 +13,10 @@
 #define INTR_RANDOM_MASK       (0x40070010UL)
 #define PLIC_BASE_ADDR         (0x3c000000UL)
 #elif defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
-#define INTR_GEN_ADDR          (0x1f10060000UL)
-#define INTR_RANDOM            (0x1f10060008UL)
-#define INTR_RANDOM_MASK       (0x1f10060010UL)
-#define PLIC_BASE_ADDR         (0x1f0c000000UL)
+#define INTR_GEN_ADDR          (0x1f00060000UL)
+#define INTR_RANDOM            (0x1f00060008UL)
+#define INTR_RANDOM_MASK       (0x1f00060010UL)
+#define PLIC_BASE_ADDR         (0x1f1c000000UL)
 #endif
 
 extern int __am_ncpu;

tests/cacheoptest/llc/src/huancunop.c

@@ -3,9 +3,9 @@
 
 // naive LLC cache op test
 #if defined(__ARCH_RISCV64_XS_SOUTHLAKE) || defined(__ARCH_RISCV64_XS_SOUTHLAKE_FLASH)
-#define CACHE_CTRL_BASE 0x1f00040100
-#define CACHE_CMD_BASE 0x1f00040200
-#define HART_CTRL_RESET_REG_BASE 0x1f00001000
+#define CACHE_CTRL_BASE 0x1f10040100
+#define CACHE_CMD_BASE 0x1f10040200
+#define HART_CTRL_RESET_REG_BASE 0x1f10001000
 #else
 #define CACHE_CTRL_BASE 0x39000100
 #define CACHE_CMD_BASE 0x39000200