This reverts commit adbd524e.

* All the remain_set are set to the corresponding value before entering the s_release_req state
* set remain_clr to 0 when state change from s_release_req(probe) to
  s_release_req(release)

Debug Module is allowed to accept instruction requests.

Note that in this commit, we merge CLINT, Reserved, and Debug into
one PMA entry. The reserved address (0x3801_0000 - 0x3801_ffff) is
marked as RW instead.

This is due to limited entries of PMA and should be fixed in the
future.

Rob detects interrupts before CSRs are updated. This does not cause
errors in single core, because interrupts will not change in these
cycles. However, in multi-core, interrupts may be cleared by other
cores, resulting in updating the mcause with zero interrupts. This
would cause errors in the software as the interrupt zero is reserved.

* expand id range including 2 miss entries + 1 release entries + 2
prefetch entries