- 28 8月, 2021 3 次提交
- 27 8月, 2021 6 次提交
- 26 8月, 2021 5 次提交
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由 JinYue 提交于
* This will be a problem when a RVI jal is the last instrution of a basic block. The realEndPC will greater than startAddr + 32 bytes.
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由 JinYue 提交于
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由 JinYue 提交于
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由 Lingrui98 提交于
* write ubtb meta and data at the same time * fix fallThruError method
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由 Lingrui98 提交于
* fix a bug when establishing new ftb entry with a jalr * use ftb hit signal instead of ubtb to assign entry_hit_status * move always taken logic to ftb
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- 25 8月, 2021 2 次提交
- 24 8月, 2021 5 次提交
- 23 8月, 2021 5 次提交
- 22 8月, 2021 1 次提交
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由 Lingrui98 提交于
table configs for each bank
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- 21 8月, 2021 1 次提交
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由 Lingrui98 提交于
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- 20 8月, 2021 7 次提交
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由 Lingrui98 提交于
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由 Lingrui98 提交于
[WIP] BPU: Modify BPU and Ftq interfaces fix bug calc backendRedirectCfi.shift ftq: update interface [WIP] BPU: Add lastStage function in BranchPredictionResp [WIP] BPU: Move Tage to s2 [WIP] BPU: Fix some bugs ftq: add fast enq logic [WIP] BPU: Move RAS to s2 bpu: s2 and s3 valid should consider corresponding flush signal [WIP] BPU: When s1_valid and s2_valid all false, s3 target need compare with s0_pc_reg, s3_predicted_ghit as well [WIP] BPU: Move resp.s3 assignment from Tage to RAS [WIP] BPU: Fix bug that Tage send meta in s2 [WIP] BPU: Add brOffset and jmpOffset in ubtb tage-sc: fix typos
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
* Update reservedRefillData when ibuffer fire.
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- 18 8月, 2021 5 次提交