Pipe mul

* division should still trap

Refactor exu

test,top,SimMMIO: fix timer address to match fpga implmentation

Soft mdu

* uncoreclk -> coreclk

* we should re-implement it in the future

Fpga timer

* rvalid and bvalid should not be always asserted, else it may generate
  more responses than requests.
* TODO: r and b channels may be not ready when they are valid. We should
  maintain the valid bit until they are ready.

* else it will be too slow to work

test,top,SimMMIO: add uartlite stat and ctrl registers and map them t…

Axi

* this lets vivado block design able to recognize them as interfaces