Fpga pal

See merge request projectn/noop!7

* now we can run hello over Nanos-lite

Cache coherence

See merge request projectn/noop!6

* Now we can pass `nexus-am/tests/cachetest/loader.c` for the first
  function.
* We should also run PAL in Nanos-lite.
* To implement the full coherence, We still need to
  * invalidate the metadata when the probe requests hits
  * writeback the data to memory when the probe requests hits
  * shall we need to probe Icache?

* currently only support probe miss

* Now it will easily cause deadlock because the coherece probe requests
  are handled with the same pipeline of CPU access requests. When the
  Dcache is processing a miss request, it may form the following loop
  dependency:
    Icache.mem.resp -> CoherenceInterconnect.in(0).coh.resp ->
    Dcache.mem.resp -> CoherenceInterconnect (busy)
* To break the deadlock, we should give higher priority to coherence
  probe requests in L1 Cache. For example, we should add another state
  machine or pipeline to handle coherence probe requests. In this way,
  the coherence probe requests can be handled without waiting for the
  CPU access requests to finish.

README: add guide to set NEMU_HOME

See merge request projectn/noop!5

Fix dep

See merge request projectn/noop!4

Emu

See merge request projectn/noop!3

* now we can pass the image used in AXI4RAM as an argument of emu

Misc

See merge request projectn/noop!2

* it seems faster than sbt during the start time

Simplebus soc

See merge request projectn/noop!1

* now the name of RTL module in the block design becomes NOOPSoC

* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
  SimpleBusUH

* Previously firrtl complains about `java.util.NoSuchElementException:
  None.get`. Now it is temporarily fixed by `Flipped(Flipped(_type))`

* in the future we will support cache coherence

* chisel 3.2 supports userBits == 0