* coh should have higher priority to acquire the lock, since coh
  request will block normal request in CoherenceInterconnect

* But this yields bad timing result on FPGA, since we directly use the
  rdata from SRAM to achieve forwarding. Maybe we should move the
  forwarding logic to s3 by recording the write data if it write the
  same set as s2.

* When the ProbeStage is reading dataArray, s3 may also updating
  the same set of the dataArray, causing wrong rdata for coh.
* A solution is to add lock to guarantee miss handling in s3 and
  ProbeStage can not be active at the same time.

* this solves the interference from coh