* mq: remove usage of raw_data

* fix addr width

* ci: check verilog of MissEntry

* add an extra check to disable using of refill_data_raw in missentry
* check it when generating XSTop.v

* util: fix L2DB exists under FPGAPlatform

* util: fix L2DB exists under FPGAPlatform #2

* bump CPL2: fix sinkC

* scripts: add AddrParser py

* bump CPL2 after another PR

* fix tl d fwd at s2

* add val s0_remLoadHigherPriorityReplaySelMask

* reorder nuke priority

* set blocking true when enq

* add tlb miss wakeup logic

* remove blockByTlbMiss

* fix missqueue enq cancel

The error scenario is:
there are two load instructions, and both wants to enter the missqueue,
ldu0's load has highest priority, can enter the missqueue,
but it is canceled, so for this cycle,
there is no miss request served by missqueue,
ldu1's load has the same physical address of ldu0's load,
ldu1's load thinks it has also been served by missqueue, becacuse it
saw ldu0's load has been served, but without taking cancel signal into
consideration.

* when considering cancel, use the cancel signal in missqueue instead of
  io.req.bits.cancel

---------
Co-authored-by: Nlixin <1037997956@qq.com>

For better performance under L2 Evict@Refill feature

* bump difftest,utility: support --dump-select-db tableNameList

* mk: when WITH_CHISELDB=1, set EnableChiselDB in DebugOptions to true

* bump CPL2: for A miss, choose way when refill, then release

* bump utility: fix chiselDB

* bump CPL2: fix C blocking condition

assertion in Monitor of s1/s3 set blocking
conflicts with C blocking logic
update C blocking modifications in fix-timing

* bump CPL2: fix occWays in ReqBuf

* bump CPL2: fix multiple bugs

* bump CPL2: fix Get/Hint does not read dir and replace at refill

* bump CoupledL2: fix C&D firing logic for Get

* bump CPL2: fix Get problem

* bump CPL2: fix retry

* tmp: try modify L3 probeack logic to avoid verilator bug

* bump CPL2: fix assertion

* Bump CPL2: probe toB should write probeAckData to DS

* Bump Utility

* Bump HuanCun: use param to fix probeack logic under verilator bug

* scripts: add L2 MainPipe-DB parser.sh and helper.py

* bump CPL2: update to master with Evict@Refill

* bump CPL2: misc - fix connection

* bump CPL2 to master

* scripts: give l2DB parser scripts more decent filename

* bump cpl2

Vector load/store queue, exception handling and writeback will be improved later

---------
Co-authored-by: lulu0521 <majianlu_0521@163.com>

* perf: add counter

* dcache hit rate = s2_dcache_real_miss_first_issue / s2_in_fire_first_issue

* fix: fix compile

* utils: support perf rolling data collection through chiseldb

* perf: add ipc rollingperf

* script: add rolling plot script

* param: disable rollingdb by default

* misc: fix typo

Prefix the port signal name of memblock to indicate the direction and source.

* fix probe_ttob_check_resp timing

* move probe_ttb check to mainpipe s2, get resp in s3

* fix main_pipe_req timing

* remove fastarbiter

* fix prefetcher timing

* remove select invalid way first

* MemBlock: fix timing

* add  redirectCancelCount

* correct canAccept

* fix loadQueueReplay select timing

* rename sleepIndex

* rename selectIndexOH

---------
Co-authored-by: Nlixin <1037997956@qq.com>

Co-authored-by: NYanqin Li <liyanqin@bosc.ac.cn>

* PTW: Move PTW to MemBlock

Move itlbrepeater to Frontend and MemBlock, dtlbrepeater to MemBlock,
L2 TLB (PTW) and ptw_to_l2_buffer to Memblock for better partition.

* MMU: Fix sfence delay to synchronize modules

* LQ: wakeup ld by cache miss used TL D channel refill signal

* rename sourceId

* add Grant ack for tl d channel wakeup

* rename refill

* tl d channel wakeup when enq

Co-authored-by: NbugGenerator <1773908404@qq.com>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NHaoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn>

when valid count reaches StoreBufferSize, do eviction
* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used
* It should remove store stall we observed in lbm.
* Add the dynamic prioritization mechanism between load stores.
* Detects the number of valid entries in the storeQueue, and if it is larger than ForceWriteUpper, forces the sbuffer to be written down to Dcache until the number of valid entries in the storeQueue is lower than ForceWriteLower.

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
Co-authored-by: Nsfencevma <35756813+sfencevma@users.noreply.github.com>

* Memblock: Add load/store 128 bits datapath

---------
Co-authored-by: lulu0521 <majianlu_0521@163.com>

* Memblock: fix bug of raw addr match

* Memblock, LoadUnit: Fix Vector RAW paddr match

---------
Co-authored-by: lulu0521 <majianlu_0521@163.com>

* bump coupledL2

* fix hint counter

* hint: make it more accurate

* cache missed load has highest priority in load s0

* add isHWPrefetch condition for l1 prefetch

* fix s2_ld_valid_dup

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* fix load exception buffer enqueue condition

* fix load exception buffer enqueue condition

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

* add new ldu and stu

* add fast replay kill at s1

* fix pointer chasing cancel

* pick flushpipe_rvc

* merge flushpipe_rvc

* fix s3_cache_rep and s3_feedbacked

* fix fast replay condition

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>