Instead of using io.req.bits as a index to search in valid array, we use
s1_addr register to keep the valid read from valid register array.

Store whole cache line in one SRAM.
Let backend engineers manually split it into smaller banks.

Change icachemisQueueEntryIdWidth to icacheMissQueueEntryIdWidth.

We use single port SRAM, read and write in the same cycle is not
allowed.

in one cycle.