* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* l2tlb: opt timing of req_addr_low to page cache

* l2tlb: change signal name from first/secode to stage1/2

* l2tlb: page cache forgot satp.changed before, add it

* util: update DataHoldBypass, more general

* util: update PipelineConnect, add block signal

* l2tlb: page cache now need 3 cycle: in/read | read back/ecc check | out

* l2tlb: set ecc block to XLEN(64)

* l2tlb: when ecc error, dont hit. do it same cycle

* tlb: optimize repalce io, for covering refill and better timing

Now uncache store may commit together with cached store. For example:

0: sd to uncache_addr
4: sd to cache_addr
8: sd to cache_addr
May commit in the same cycle.

It should eliminate wrong assertion in xalancbmk.

* InstrUncache: change into 1 instruciton logic

* Frontend: add MMIO fetch port

* IFU: flush pipeline and only pass 1 instruction to backend when
finding the address is mmio

* BPU: set the resetVector to 10000000

* Frontend: connect ifu.uncache to instrUncache

* IFU: Fix conflict with master

* IFU: fix mmio instruction prediction problem

* IFU: fix tlb af only hold 1 cycle

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

* bump difftest & huancun

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset

In the latest version of dcache, replace pipe is blocked by main pipe according to set, because replace and store/probe should not try to modify data or meta at the same time, which might result in inconsistency between data and meta. For performance reasons, replace is blocked by store, not the other way around, because replace can be delayed so it can bring dirty data written by store down to L2.

Now this consideration brings another dead-lock. Store buffer keeps sending store request without a break, so main pipe stays occupied handling store. In the meantime, miss queue rejects these store request so store buffer keeps replaying all the time. Replace pipe cannot advance because of set conflict with main pipe, so the corresponding miss entry cannot be released and keeps rejecting new store request.

To break this dead-lock, this pull request tries to set replace pipe higher priority than main pipe, and let write-back queue handle consistency between data and meta if a store interrupts.

Modify FTB replacement strategy to PLRU

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just flush it all, don't care asid.
3. when hit check, check asid.
4. when asid changed, flush all the inflight ptw req for safety
5. simple asid unit test:
asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa

* ASID: make satp's asid bits configurable to RW
* use AsidLength to control it

* ASID: implement asid refilling and hit checking
* TODO: sfence flush with asid

* ASID: implement sfence with asid
* TODO: extract asid from SRAMTemplate

* ASID: extract asid from SRAMTemplate
* all is down
* TODO: test

* fix write to asid

* Sfence: support rs2 of sfence and fix Fence Unit
* rs2 of Sfence should be Reg and pass it to Fence Unit
* judge the value of reg instead of the index in Fence Unit

* mmu: re-write asid

now, asid is stored inside sram, so sfence just flush it
it's a complex job to handle the problem that asid is changed but
no sfence.vma is executed. when asid is changed, all the inflight
mmu reqs are flushed but entries in storage is not influenced.
so the inflight reqs do not need to record asid, just use satp.asid

* tlb: fix bug of refill mask

* ci: add asid unit test
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

This commit changes how de-allocation is done in RefCounter. One cycle
after we update the reference counters, the free registers are released
to the freelist.

Previous version creates a critical path, starting from deallocate ports
and ending at freelist registers. This commit adds one more cycle in the
allocation --> updating reference counters --> freeing physical
registers --> allocation loop.

Now we merge them for timing opt, unit test to be added later

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* IFU: add performance counters and mmio af

* icache replacement policy moniter

* ifu miss situation moniter

* icache miss rate

* raise access fault when found mmio req

* Add framework for seperated main pipe and reg meta array

* Rewrite miss queue for seperated pipes

* Add RefillPipe

* chore: rename NewSbuffer.scala

* cache: add CacheInstruction opcode and reg list

* CSR: add cache control registers

* Add Replace Pipe

* CacheInstruction: add CSRs for cache instruction

* mem: remove store replay unit

* Perf counter to be added
* Timing opt to be done

* mem: update sbuffer to support new dcache

* sbuffer: fix missqueue time out logic

* Merge remote-tracking branch 'origin/master' into dcache-rm-sru

* chore: fix merge conflict, remove nStoreReplayEntries

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Rewrite main pipe

* ReplacePipe: read meta to decide whether data should be read

* RefillPipe: add a store resp port

* MissQueue: new req should be rejected according to set+way

* Add replacement policy interface

* sbuffer: give missq replay the highest priority

Now we give missqReplayHasTimeOut the highest priority, as eviction
has already happened
Besides, it will fix the problem that fix dcache eviction generate logic
gives the wrong sbuffer id

* Finish DCache framework

* Split meta & tag and use regs to build meta array

* sbuffer: use new dcache io

* dcache: update dcache resp in memblock and fake d$

* Add atomics processing flow

* Refactor Top

* Bump huancun

* DCacheWrapper: disable ld fast wakeup only when bank conflict

* sbuffer: update dcache_resp difftest io

* MainPipe: fix combinational loop

* Sbuffer: fix bug in assert

* RefillPipe: fix bug of getting tag from addr

* dcache: ~0.U should restrict bit-width

* LoadPipe: fix bug in assert

* ReplacePipe: addr to be replaced should be block-aligned

* MainPipe: fix bug in required coh sending to miss queue

* DCacheWrapper: tag write in refill pipe should always be ready

* MainPipe: use replacement way_en when the req is from miss queue

* MissQueue: refill data should be passed on to main pipe

* MainPipe: do not use replacement way when tag match

* CSR: clean up cache op regs

* chore: remove outdated comments

* ReplacePipe: fix stupid bug

* dcache: replace checkOneHot with assert

* alu: fix bug of rev8 & orc.b instruction

* MissQueue: fix bug in the condition of mshr accepting a req

* MissQueue: add perf counters

* chore: delete out-dated code

* chore: add license

* WritebackQueue: distinguish id from miss queue

* AsynchronousMetaArray: fix bug

* Sbuffer: fix difftest io

* DCacheWrapper: duplicate one more tag copy for main pipe

* Add perf cnt to verify whether replacing is too early

* dcache: Release needs to wait for refill pipe

* WritebackQueue: fix accept condition

* MissQueue: remove unnecessary assert

* difftest: let refill check ingore illegal mem access

* Parameters: enlarge WritebackQueue to break dead-lock

* DCacheWrapper: store hit wirte should not be interrupted by refill

* Config: set nReleaseEntries to twice of nMissEntries

* DCacheWrapper: main pipe read should block refill pipe by set
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLinJiawei <linjiav@outlook.com>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
Co-authored-by: Zhangfw <471348957@qq.com>

commitCount has been delayed for 1 cycle, so we need to check
uncacheState 1 cycle earlier

* l2tlb: fix bug that miss queue full causes enq dropped

* l2tlb: set l2tlb miss queue to 1 + base size. 10 actually

* l2tlb: optimize l2tlb prefetcher, able to across 2MB

* bump huancun

Previously difftest uses the extra 32 read ports of regfile and it is
disabled by default under FPGAPlatform. However, when FPGAPlatform is
enabled, we also drop the right 32 read ports and it causes errors.

tage: synchronize base table update valid and data signals

sfence_latch will only be reset by mem_resp_done, which has higher priority than set by sfence

previously we may use random data from ftq meta sram, and now we fixed this issue

This commit removes the update logic for ref counter 0.

For simplicity, we don't count the number of references for physical
register 0. It should never be released to freelist.

Previously we track register 0's references. It works fine but it makes
the performance counters confusing because it may increase to a large
number. It never causes real issues.

This commit removes lsrc usages in the fence unit and lsrc is no longer
needed after an instruction is renamed. It helps timing and area.

lsrc is placed in imm at rename stage (the last stage we need lsrc).
They are extracted in the fence unit. Imm needs to go through the
pipelines because Jump needs it (and we re-use it for lsrc).

This commit fixes the walkCounter value in Rob when every instruction is
flushed.

For example, when rob is full and the head instruction causes an
exception, the redirect robIdx is the deqPtr. In this case,
currentWalkPtr is enqPtr - 1.U and redirectWalkDistance is RobSize - 1.
Since exceptions flush the instruction itself, flushItSelf is true.B.
Previously we use `+` to count the walk distance and it causes overflows
when RobSize is power of 2. We change it to `+&` to allow walkCounter to
be RobSize. The width of walkCounter also needs to be changed.

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

* Update PrintControl transform

* CI: add fatal/fwrite check

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

* storeset: fix waitForSqIdx generate logic

Now right waitForSqIdx will be generated for earlier store in the same
dispatch bundle.

* mdp: add strict wait mode

When loadWaitStrict && loadWaitBit, load will wait in rs until all
older store addr calculation are finished.

* chore: add storeset_load_strict_wait counter

* bump difftest