This commit adds load balance support for two dispatch ports, between 0
and 2, 1 and 3, etc.

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction
Co-authored-by: Zhangfw <471348957@qq.com>

This commit adds IOs for performance counters in reservation stations.
Only `full` is included for now.

* mem: update block load logic

Now load will be selected as soon as the store it depends on is ready,
which is predicted by Store Sets

* mem: opt block load logic

Load blocked by std invalid will wait for that std to issue
Load blocked by load violation wait for that sta to issue

* csr: add 2 extra storeset config bits

Following bits were added to slvpredctl:
- storeset_wait_store
- storeset_no_fast_wakeup

* storeset: fix waitForSqIdx generate logic

Now right waitForSqIdx will be generated for earlier store in the same
dispatch bundle

bump difftest and add lightSSS wave dump for CI

This commit changes how dispatch ports (regfile ports) are connected to
reservation station ports:

INT regfile:
* INT(0-1) --> ALU0, MUL0, JUMP
* INT(2-3) --> ALU1, MUL0
* INT(4-5) --> ALU2, MUL1
* INT(6-7) --> ALU3, MUL1
* INT(8)   --> LOAD0
* INT(9)   --> LOAD1
* INT(10)  --> STA0
* INT(11)  --> STA1
* INT(12)  --> STD0
* INT(13)  --> STD1

FP regfile:
* FP(0-2)  --> FMA0, FMISC0
* FP(3-5)  --> FMA1, FMISC0
* FP(6-8)  --> FMA2, FMISC1
* FP(9-11) --> FMA3, FMISC1
* FP(12)   --> STD0
* FP(13)   --> STD1

* [WIP] PMP: add pmp to tlb & csr(ptw part is not added)

* pmp: add pmp, unified

* pmp: add pmp, distributed but same cycle

* pmp: pmp resp next cycle

* [WIP] PMP: add l2tlb missqueue pmp support

* pmp: add pmp to ptw and regnext pmp for frontend

* pmp: fix bug of napot-match

* pmp: fix bug of method aligned

* pmp: when write cfg, update mask

* pmp: fix bug of store af getting in store unit

* tlb: fix bug, add af check(access fault from ptw)

* tlb: af may have higher priority than pf when ptw has af

* ptw: fix bug of sending paddr to pmp and recv af

* ci: add pmp unit test

* pmp: change PMPPlatformGrain to 6 (512bits)

* pmp: fix bug of read_addr

* ci: re-add pmp unit test

* l2tlb: lazymodule couldn't use @chiselName

* l2tlb: fix bug of l2tlb missqueue duplicate req's logic

filt the duplicate req:
old: when enq, change enq state to different state
new: enq + mem.req.fire, more robust

* pmp: pmp checker now supports samecycle & regenable

Make bank conflict feedback 1 cycle earlier

* bump chisel to 3.5.0-RC1

We don't want to use SNAPSHOT version any more because we don't know
what will happen when we wake up in the morning.

* misc: remove TMA_* to avoid conflicts

get ecc result at the same cycle, may have timing problem, deal with
it later...
when ecc error happens, 'miss' the req and flush the entry next cycle

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to ld func unit. Then, we modified some interaction signals in ordinary Load steps.

FastUops from ExuBlock contain some outside function units, which should
be removed.

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at decode stage and bypass write data
from this clock cycle to the read data at next cycle.

For write, we latch the write request and process it at the next cycle.

* This commit add risc-v cryptography extension subset(zknd zkne zknh zksed zksh)
- Rename bmu to bku
- Add crypto instruction in Mdu -> bku
- Store immediate into mdu RS

* ci: add riscv-crypto test

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does not support instruction fusion, disable that
in XiangShan if runahead is needed

* runahead: bump version

* difftest: bump version to support runahead

* chore: bump huancun to make ci happy

* chore: fix wrong submodule url

* difftest: bump version

BREAKING CHANGE: nemu update_config api has changed

This commit adds fpStateReadOut and fpStateReadIn ports to Scheduler to
support reading fp reg states from other schedulers.

It should have better timing because now ExuBlock(0) has only int
regfile and busytable. This block does not need fp writeback any more.

* Fix a div 1 bug
* Fix a typo

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)