This fixed two problems:
1. for load, we can select word and do ECC in stage 1, this release the
timing pressue in stage 2.
2. for MainPipe, when stalled by WritebackUnit, we can latch tag and
data together. This fixed bugs caused by stall.

When load miss are merged at refill_done,
we forget to refill to loadQueue.

Wait 16 cycles before replaying the req.
This gives others chances to use MainPipe.

improve fairness and avoid starvation.

and Writeback req.

 those written by store in flight

Should select the correct row from refill data.

We require that: for AcquireBlock, L2 should always gives us GrantData, not Grant.
Add assertions to catch violations.

do not get it from io.req.bits.
They may change!!!

Also: blocked same block miss req and same block reqs.

This satisfies TL spec page 68:
Release:
master should not issue a Release if there is a pending Grant on the block.
Once the Release is issued, the master should not issue ProbeAcks, Acquires,or further Releases
until it receives a ReleaseAck from the slave acknowledging completion of the writeback.

fix pipeline flush bug

If we give priority to LoadPipe, MainPipe may be blocked.
If there is a large number of load miss, they fail to enter MissQueue
due to MainPipe blocked. They will continuously replay, which further
blocks MainPipe.
In the end, it becomes a deadlock.
TODO: do RR on both meta array and data array, ensure that get meta
array and data array at the same cycle.

Or too many store will fully occupy MainPipe and cause all others starve
to death, which leads to deadlock.

Now, it can compile.

No longer needed, replaced by "-m".

Trace debug

div: don't accept new request when it's cancelled

SRAMTemplate: fix wmask and update license