- 01 12月, 2021 3 次提交
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由 Yinan Xu 提交于
* bku: add one more cycle of latency * bku: support pipeline stalls
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由 Li Qianruo 提交于
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由 Jiawei Lin 提交于
* Clean up project dependencies * Update README * Fix typo
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- 30 11月, 2021 3 次提交
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由 William Wang 提交于
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由 Yinan Xu 提交于
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由 wakafa 提交于
* bump huancun * bump huancun * bump huancun
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- 29 11月, 2021 5 次提交
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由 zhanglinjuan 提交于
* dcache: merge replace pipe with main pipe for timing reason * MainPipe: fix bug in s3_fire * MainPipe: fix bug in delay_release sent to wbq * MainPipe: fix bug in blocking policy * MainPipe: send io.replace_resp in stage 3 * MainPipe: fix bug in miss_id sent to wbq * MainPipe: fix bug Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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由 Steve Gou 提交于
bpu timing optimization
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由 William Wang 提交于
* sbuffer: do flush correctly while draining sbuffer * mem: disable EnableFastForward for timing reasons * sbuffer: optimize forward mask gen timing * dcache: block main pipe req if refill req is valid Refill req comes from refill arbiter. There is not time left for index conflict check. Now we block all main pipe req when refill req comes from miss queue. * dcache: delay some resp signals for better timing * dcache: optimize wbq enq entry select timing * dcache: decouple missq req.valid to valid & cancel * valid is fast, it is used to select which miss req will be sent to miss queue * cancel can be slow to generate, it will cancel miss queue req in the last moment * sbuffer: optimize noSameBlockInflight check timing
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由 Jay 提交于
* bump difftest
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由 Yinan Xu 提交于
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- 28 11月, 2021 1 次提交
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由 Jay 提交于
* ICache: metaArray & dataArray use bank interleave * ICache: add bank interleave * ICache: add parity check for meta and data arrays * IFU: fix bug in secondary miss * secondary miss doesn't send miss request to miss queue * ICache: write back cancled miss request * ICacheMissEntry: add second miss merge * deal with situations that this entry has been flushed, and the next miss req just requests the same cachline. * ICache: add acquireBlock and GrantAck support * refact: move icache modules to frontend modules * ICache: add release surport and meta coh * ICache: change Get to AcquireBlock for A channel * rebuild: change ICachePara package for other file * ICache: add tilelogger for L1I * ICahce: add ProbeQueue and Probe Process Unit * ICache: add support for ProbeData * ICahceParameter: change tag code to ECC * ICahce: fix bugs in connect and ProbeUnit * metaArray/dataArray responses are not connected * ProbeUnit use reg so data and req are not synchronized * RealeaseUnit: write back mata when voluntary * Add ICache CacheInstruction * move ICache to xiangshan.frontend.icache._ * ICache: add CacheOpDecoder * change ICacheMissQueue to ICacheMissUnit * ProbeUnit: fix meta data not latch bug * IFU: delete releaseSlot and add missSlot * IFU: fix bugs in missSlot state machine * IFU: fix some bugs in miss Slot * IFU: move out fetch to ICache Array logic * ReleaseUnit: delete release write logic * MissUnit: send Release to ReleaseUnit after GAck * ICacheMainPipe: add mainpipe and stop logic * when f3_ready is low, stop the pipeline * IFU: move tlb and array access to mainpipe * Modify Frontend and ICache top for mainpipe * ReleaseUnit: add probe merge status register * ICache: add victim info and release in mainpipe * ICahche: add set-conflict logic * Release: do not invalid meta after sending release * bump Huancun: fix probe problem * bump huancun for MinimalConfig combinational loop * ICache: add LICENSE for new files * Chore: remove debug code and add perf counter * Bump huancun for bug fix * Bump HuanCun for alias bug * ICache: add dirty state for CliendMeta
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- 27 11月, 2021 1 次提交
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由 Lingrui98 提交于
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- 26 11月, 2021 6 次提交
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由 Lingrui98 提交于
* use one hot muxes for ftb read resp * generate branch history shift one hot vec for history update src sel and update for all possible shift values
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由 Yinan Xu 提交于
This commit optimizes instruction fusion detection logic for fused addw{byte, bit, zexth, sexth}, mulw7, and logic{lsb, zexth} instructions. Previously we use fuType and fuOpType from the normal decoder, and this incurs a bad timing. Now we change the detection logic to use only the raw instructions. Though the fused instruction still uses the fuOpType from the normal decoder, there should be only serveral MUXes left.
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由 Steve Gou 提交于
ftq: optimize ifu request timing
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由 rvcoresjw 提交于
update hpmevent defalt value and write mask; modify fetch trigger res…
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由 Yinan Xu 提交于
This commit changes how isFreed is calculated. Instead of using refCounter in the next, we compute it at this cycle and RegNext it.
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由 Lingrui98 提交于
* decouple fall through address calculating logic from the pftAddr interface * let ghr update from s1 has the highest priority * fix the physical priority of PhyPriorityMuxGenerator
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- 25 11月, 2021 2 次提交
- 24 11月, 2021 3 次提交
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由 rvcoresjw 提交于
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由 rvcoresjw 提交于
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由 William Wang 提交于
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- 23 11月, 2021 2 次提交
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由 William Wang 提交于
* mdp: implement SSIT with sram * mdp: use robIdx instead of sqIdx Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a "speculatively assigned" sqIdx, as it is hard to track store insts in dispatch queue. Yet we can still use "speculatively assigned" robIdx for memory dependency predictor. For now, memory dependency predictor uses "speculatively assigned" robIdx to track inflight store. However, sqIdx is still used to track those store which's addr is valid but data it not valid. When load insts try to get forward data from those store, load insts will get that store's sqIdx and wait in RS. They will not waken until store data with that sqIdx is issued. * mdp: add track robIdx recover logic
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由 Yinan Xu 提交于
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- 21 11月, 2021 1 次提交
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由 Jiawei Lin 提交于
* misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2
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- 18 11月, 2021 4 次提交
- 17 11月, 2021 2 次提交
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由 Steve Gou 提交于
bpu: extract wrbypass to be a module
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由 Li Qianruo 提交于
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- 16 11月, 2021 5 次提交
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由 Lingrui98 提交于
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由 zhanglinjuan 提交于
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由 Jiawei Lin 提交于
* FDivSqrt: use hierarchy API to avoid dedup bug * Dedup: use hartId from io port instead of core parameters * Bump fudian
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由 Steve Gou 提交于
BPU: Change the u in the ITTAGE from register to SRAM implementation
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由 Jay 提交于
This bug happens when a branch prediction results in a fetch to MMIO space, and the backend flush could not flush the MMIO, thus results in blocking.
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- 15 11月, 2021 2 次提交