- 09 11月, 2022 35 次提交
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由 Jenius 提交于
* <bug-fix> IFU: cancel lastHalf for miss prediction * <bug-fix> ICacheMainPipe: latch tlb resp for stall * <bug-fix> only tlb_slot.valid can raise has_latch
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由 Jenius 提交于
* copy Ftq to ICache read valid signal * move sram read data and miss data selection to IFU (after predecode)
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由 Jenius 提交于
* copy address select signal for every copied port * add 1 more copy for itlb request use * add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch
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由 Jenius 提交于
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由 Jenius 提交于
* this bug is caused by trigger wait_state for a hit pmp af req
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* <bug-fix>: fix port_1_read_0 condition
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由 Jenius 提交于
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
* should use RegNext on ftq_pc_mem rdata with the wrapper implementation now
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由 Jenius 提交于
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
ftq, ctrl: fix newest_target logic, pass it to ctrlblock, remove jalrTargetMem and read target from pc_mem
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* add diff for upate_target and pc_mem result
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles
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由 Lingrui98 提交于
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由 Jenius 提交于
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由 Lingrui98 提交于
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由 Jenius 提交于
* FtqToICache add bypass write signal and use bypass signal
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由 Jenius 提交于
* IFU: ignore ICache access bundle * ICacheMainPipe: expand meta/data access output to 4 identical vector output, each output is connected to a copied register trigger by FTQ requests * IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical vector output, and each output is triggered by the same signal group
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由 Jenius 提交于
* add ICachPartWayArray to wrap a part-way module * SRAM array array_0 array_1: width × 1/4 and depth stay unchanged
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由 Jenius 提交于
* separate ifu req and icache req for timing optimization * both ifu ftq_req_ready and icache ftq_req_ready depend on each other * ifu and icache has pc_mem register [WIP]ICacheMainPipe: add copied registers [WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied [WIP] FTQ: delete outside bypass
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由 Yinan Xu 提交于
* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq * ctrl: add data modules for pc and jalr_target This commit adds two data modules for pc and jalr_target respectively. They are the same as data modules in frontend. Should benefit timing. * jump: reduce pc and jalr_target read latency * ftq: add predecode redirect update target interface, valid only on ifuRedirect * ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
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- 08 11月, 2022 2 次提交
- 02 11月, 2022 3 次提交