- 14 4月, 2023 5 次提交
- 12 4月, 2023 2 次提交
- 10 4月, 2023 2 次提交
- 09 4月, 2023 2 次提交
- 06 4月, 2023 2 次提交
- 05 4月, 2023 4 次提交
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由 Xuan Hu 提交于
* wakeup can take effect only when valid is assert
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由 Xuan Hu 提交于
* support float memory load/store * refactor regfile read parameters * replace `numSrc` with `numRegSrc` to notice the src data being from regfile * refactor BusyTable read port * make int/vf BusyTable have the same number of read ports to simplify connection in Dispatch2Iq * the unused read port will be optimized * regular IQSize parameters * split writeback port for scheduler into two kinds by reg types
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由 Xuan Hu 提交于
* srcType of store data is from dispatch2iq.io.out(x).bits.srcType(1)
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由 Xuan Hu 提交于
* `rsIdx` and `isFirstIssue` should be guarded by valid instead connecting from IQ to memBlock directly.
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- 30 3月, 2023 1 次提交
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由 Xuan Hu 提交于
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- 28 3月, 2023 1 次提交
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由 Xuan Hu 提交于
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- 27 3月, 2023 1 次提交
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由 Xuan Hu 提交于
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- 26 3月, 2023 1 次提交
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由 Xuan Hu 提交于
* Only dequeue common accepted inst in main deq policy * Add guard assert in exe unit to avoid some inst not dispatched to fu
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- 21 3月, 2023 1 次提交
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由 fdy 提交于
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- 15 3月, 2023 1 次提交
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由 Xuan Hu 提交于
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- 14 3月, 2023 2 次提交
- 12 3月, 2023 9 次提交
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由 Xuan Hu 提交于
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由 Xuan Hu 提交于
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由 Xuan Hu 提交于
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由 Xuan Hu 提交于
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由 Xuan Hu 提交于
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由 Xuan Hu 提交于
Add the Busy register in exe units to indicate that new instructions cannot be received, but it does not allow the exe unit to be pipelinable. Todo: make exe unit pipelinable.
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由 Xuan Hu 提交于
Todo: revert this when mem block connected
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由 Xuan Hu 提交于
The nanhu version make div valid signal ahead of data by one cycle to optimize timing of wbArbiter. We make `io.valid` signal assert at the same time of data valid as normal now, and add `io.validNext` signal which asserts one cycle ahead of `io.valid`.
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由 Xuan Hu 提交于
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- 06 3月, 2023 1 次提交
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由 Xuan Hu 提交于
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- 12 2月, 2023 4 次提交
- 11 2月, 2023 1 次提交
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由 Xuan Hu 提交于
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