* Revert "ftq: fix unintended commitStateQueue left out (#1920)"

This reverts commit 948933da.

* Revert "break ifuwbptr dependency"

This reverts commit 2448f137.

* ftq: revert #1875, #1920

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* bump difftest, assign empty value to OBJCACHE

* local-ci: mkdir for wave/perf at run-mode

Usage:
1. run ci test
`python3 scripts/local_ci.py --xs-path $(pwd) --run`

2. print ci test name
`python3 scripts/local_ci.py --xs-path $(pwd) --show-test`

3. print ci test command into splited sh files. Run the sh manualy.
`python3 scripts/local_ci.py --xs-path $(pwd)`
More Params:
  --sh-path: default is xs-path/ci-sh.

Other Params:
  --pick-test MC: only run 'EMU - MC'
  --numa: use numa ctrl, require eypc
  --head-sha: magic word, default is today's date
  --nemu-home/--am-home: don't know if it is used

* bump utility and difftest

Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------
Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
  clear intrGen's intr: Stop pass interrupt. A mmio write.
  clear plic claim: complete intr. A mmio write.
  read plic claim to check: claim should be 0. A mmio read.
The corner case:
  intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

SimTop: add support for Constantin

dtlb: set pf-tlb's ready to be True by default

sms,ldu,dcache: prefetch to l1 framework & new load flow arb

Software prefetch flow (from storeprefetch uop) will not be replayed
unless tlb reports a miss. In that case, software prefetch flow behaves
like an normal tlb missed load.

Hardware prefetch flow will never be replayed.

This commit refactors ldu load_s0 load flow arbitor logic.

Now there are 6 load flow sources, which are (priority high -> low):

src0: load replayed by LSQ (io.lsqOut)
src1: hardware prefetch from prefetchor (high confidence) (io.prefetch)
src2: int read / software prefetch first issue from RS (io.in)
src3: vec read first issue from RS (TODO)
src4: load try pointchaising when no issued or replayed load (io.fastpath)
src5: hardware prefetch from prefetchor (high confidence) (io.prefetch)

Co-authored-by: NZhangZifei <1773908404@qq.com>

TODO: ldflow from prefetch to be added to ldflow select logic