* Top: remove extra axi ID bits

* Re-add AXI4UserYanker
Co-authored-by: NLinJiawei <linjiav@outlook.com>

previously the biggest problem was using '+' instead of '+&' to
do sums

* LoadUnit: generate fastUop in load_s1

* RS/Load: add load to fast wakeup when cache hit, while maintain its slow

* RS: remove legacy assert that doesn't work for load has fast and slow

* LoadUnit: fix bug that fastUops's valid forgets load_s1.io.in.valid

* MemBlock: fix bug of loadUnit's fast and slow connect

IPC of coremark 10 cycles raise from 1.63 to 1.70

* RS: RegNext srcUpdate to use it at next cycle

* RS: add param EnableLoadFastWakeUp and set default to false
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* L1I/L1+:  Add performance counters for each way.

* Replacement: fix that lfsr always changes in random.

* TLB&PTW: add replace perf count

* PTW: remove set's perf count, just way's

* PTW: fix bug that puts perf inside when

* TLB&PTW: add access perf count

DCache: rearrange dcache array and set write priority higher than read

* RS: add many rs's perf cnter

* RS: add param myName for submodule name

* RS: set Integer&Mem block's rs' srcLen to XLEN

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog
Co-authored-by: NLinJiawei <linjiav@outlook.com>

Previously, we use !flushPipe to reduce serveral or gates.
However, when an instruction has instruction page fault or access fault,
the instruction may be decoded as any instructions, which possibly generates flushPipe.
Thus, previously an instruction with exceptions may trigger a flushPipe instead of exceptions.

Now we use exceptionVec.asUInt.orR to see whether it has exceptions.

This reverts commit 1c6ad6d0.

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* ifu: add perf counters

* Perf: Add loopPredictor perf counters

* sc: fix perf logics
Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>
Co-authored-by: Nzoujr <18870680299@163.com>

* NewSbuffer: warp sbuffer data

* NewSbuffer: fix data write
Co-authored-by: NLinJiawei <linjiav@outlook.com>

* Replacement: fix way method bugs

We do state change when calling way method, but in lack of a signal to
inform whether it is necessary to do state change, this might cause
problem.

* ICache: use new replacement method

* L1plusCache: change replacement method

* L1plusCache: add performance counters.

* L1plusCache: fix performance bug.

ICache miss penalty increases because that we miss the access method
in L1plusCache for replacement :)

DCache: rewrite pipeline and dcache array arrangement

* xscore: remove reg and logic in xscore top module

* XSCore: remove logic in top module

* Fp/Int block: fix write back bug
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* RS: optimize numExist signal

* RS: fix some typo

* RS: optimize deq logic for block-nonfeedback rs

ifu: opt timing of redirect ghist

* NewSbuffer: allow multi-inflight dcache request to improve performance

* NewSbuffer: fix bugs in replace && add more debug print

* SbufferTest: update sbuffer test

* Replacement: change state in way method.

* State change is also needed when miss occurs, otherwise we will choose
a way that has been just refilled into cache as the victim.

* Optimize ctrlblock timing (#620)

* CtrlBlock: delay exception flush for 1 cycle

* CtrlBlock: delay load replay for 1 cycle

* roq: delay wb from exu for one clock cycle to meet timing

* CtrlBlock: fix pipeline bug between decode and rename
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* L1plusCache: use plru replacement policy.

* ICache: fix mmio bugs

1. MMIO cut helper uses packet align logic
2. still send req to uncache when flush

* ICache: change packet from mmio

use packet align as the mem

* IntrUncache: fix state bug

state will change into s_invalid and get stuck

* fix Registers that not being initiated