We pass redirect ghist directly to a mux, whose output is connected
to bpu.s1_hist, so that the delay of three cascaded 64-bit-wide 2-1
mux could be saved

* Backend: fix some bugs related to exu write

* Roq: revert to perv verision

* Fix fp write back bugs

* LSQ: use async vaddrModule

* StoreQueue: opt mmio writeback valid timing

* LSQ: opt vaddr read ptr gen timing

* chore: remove unnecessary script

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

perf: Add perf counters for bpu

Optimize l1plus Cache and L1plus prefetcher timing.

perf: support pf-cnt dump & clean

First latch and then decode for timing consideration.

fix conflict for l1plusprefetcher

add enable IO for prefetcher and move L2 prefetcher to SoC

bug dcache deadlock

This logic causes long latency from l1+ Cache. And ready signal should
depend on itself.

For timing consideration, now we only detect ECC errors but don't
correct them.

This type of exception will only be reported when data hit in ICache and
the parity check is wrong.

It may be report as exception