* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: add mconfigptr, but hardwire to 0 now

* csr: add *BE to mstatusStruct which are hardwired to 0

* csr: fix bug of xret clear mprv

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

This commit changes the splitN algorithm for the write-back arbiter.

Previously we split the function units as follows:
(FU0 FU1 FU2) (FU3 FU4 FU5).
However, this strategy tends to group the function units with the same
type into the same arbiter and may cause performance loss.

In this commit, we change the strategy to: (FU0 FU2 FU4) (FU1 FU3 FU5).

This commit optimizes the issue grant timing when age is enabled.
Select from age and SelectPolicy are processed parallely.

* bump huancun

This commit adds an interrupt_safe flag that tracks whether an
instruction is safe for interrupts.

For example, any MMIO instruction is not safe because it changes
the external devices before write-back.

* csr: fix write mask for mstatus, mepc and sepc

This commit fixes the write mask for mstatus, mepc and sepc.

According to the RISC-V instruction manual, for RV64 systems,
the SXL and UXL fields are WARL fields that control the value of
XLEN for S-mode and U-mode, respectively. For RV64 systems, if
S-mode is not supported, then SXL is hardwired to zero. For RV64
systems, if U-mode is not supported, then UXL is hardwired to zero.

Besides, mepc[0] and sepc[0] should be hardwired to zero.

* bump difftest

* use toMeta.fire() will cause data miss match when toMeta.valid :=
req.valid

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: add Block logic for ReplacePipe

* ReplacePipe: change probe assert condition

* support Probe NToN (Probe not hit in ICache)

* ICache: fix a bug in meta_write_arb

* update id width, set io bits to do not touch
* modify dma data width from 128bits to 256 bits

* mem: delay uncache op start for 1 cycle

* dcache: decouple miss and replay signal

Now resp.miss will not depend on s2_nack_no_mshr

* lq,mem: give released flag update 1 more cycle

* chore: fix a name typo

* dcache: delay probe req for 1 cycle

* Add 1 cycle in refill pipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for peripheral port

* Fix submodule version

* sbuffer: do flush correctly while draining sbuffer

* ci: enable ci for timing-memblock branch

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we simplily block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* WritebackQueue: optimize enqueue logic fir timing

* WritebackQueue: always reject a req when wbq is full

* Revert "ci: enable ci for timing-memblock branch"

This reverts commit 32453dc4.

* WritebackQueue: fix bug in secondary_valid
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

* Filter: hit dont care asid for when asid change, flush all

* TLB: timing opt in hitppn and hitperm Mux

* l2tlb.filter: timing opt in enqueue filter logic

add one more cycle when enq to break up tlb's hit check and filter's
dup check.

so there are 3 stage: regnext -> enqueue -> issue
when at regnext stage:
  1. regnext after filter with ptw_resp
  2. do 'same vpn' check with
    1) old entries &
    2) new reqs &
    3) old reqs.
    but don't care new reqs'valid
when at enqueue stage:
  use last stage(regnext)'s result with valid signal at this stage
  to check if duplicate or not. update ports or enq ptr, et al.
  alse **optimize enqPtrVec generating logic**
  also **optimize do_iss generating logic**

* TLB: add fast_miss that dontcare sram's hit result

* L2TLB.filter: move lastReqMatch to first stage

* bku: add one more cycle of latency

* bku: support pipeline stalls

* Clean up project dependencies

* Update README

* Fix typo

* bump huancun

* bump huancun

* bump huancun

* dcache: merge replace pipe with main pipe for timing reason

* MainPipe: fix bug in s3_fire

* MainPipe: fix bug in delay_release sent to wbq

* MainPipe: fix bug in blocking policy

* MainPipe: send io.replace_resp in stage 3

* MainPipe: fix bug in miss_id sent to wbq

* MainPipe: fix bug
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

bpu timing optimization

* sbuffer: do flush correctly while draining sbuffer

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* dcache: decouple missq req.valid to valid & cancel

* valid is fast, it is used to select which miss req will be sent to
miss queue
* cancel can be slow to generate, it will cancel miss queue req in the
last moment

* sbuffer: optimize noSameBlockInflight check timing

* bump difftest