* now "--fpga-platform --dualcore" will be reserved for dualcore without
difftest

dev-prefetcher: replace stream prefetch with best-offset in L2Prefetcher

Give replay check an extra cycle (store s3)

makefile: generate memory modules and commit id when make verilog

backend,fu,CSR: clear mstatus.MPP upon reset

DecodeUnit/IFU: move RVC expander to if4

SRAMTemplate: support --infer-rw --repl-seq-mem

exu,div: set io.in.valid though the instruction is flushed

backend,busytable: update IOs and optimize timing

RS: timing optimizaton that rs enq listen to writeback other than busytable

RS: rs timing optimaziton and rename some signal && fence's timing optimization

L1plus : opt timing in valid_array read

backend,roq: RegNext isEmpty and block commits when exceptions for better timing

excitingutils: warn wires that have multiple sink|source

Icache uncache

csr: support privMode check for perfcnt regs

opt fdiv timing