This commit adds manual reset for every register in Regfile. Previously
the reset is done by add reset values to the registers. However,
physically general-purpose register file does not have reset values.

Since all the regfile always has the same writeback data, we don't need
to explicitly assign reset data.

This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cycles.

Now a load instruction can wakeup another load instruction at LOAD stage 1. When the producer load instruction arrives at stage 2, the consumer load instruction is issued to load stage 0 and using data from the producer to generate load address.

In reservation station, load can be dequeued from staged 1 when stage 2 does not have a valid instruction. If the fast load is not accepted, from the next cycle on, the load will dequeue as normal.

Timing in reservation station (for imm read) and load unit (for writeback data selection) to be optimized later.

* backend,rs: issue load one cycle earlier when possible

This commit adds support for issuing load instructions one cycle
earlier if the load instruction is wakeup by another load. An extra
2-bit UInt is added to IO.

* mem: add load to load addr fastpath framework

* mem: enable load to load forward

* mem: add load-load forward counter
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

This commit limits dequeue width of every RS to 2 for better timing.

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue. 

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
        -->          --> Scheduler --> RS

This commit adds support for multiple enqueue for load and store RS.
Also update the parameters in XSCore to avoid explicitly setting wakeup ports.

XiangShan is jointly released by ICT and PCL.

* change the number of function units in MinimalConfig
* remove some hard-wired values

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.

* change the number of function units in MinimalConfig
* remove some hard-wired values

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.