* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

* Revert "constant variable: add FPAGPlatform parameter"

This reverts commit fc2f03b7.

* constant: add FPGA init

* chiseldb: add FPGA init

* difftest: version

* chisledb: add envFPGA situation

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the constant control logic

* databases: add constant control

* constantin: afix some bug

* constantin: fix txt

* fixbug: constant control in double core

* constantin: postfix changed in `verilator.mk`

* instDB: add robIdx and some TIME signals

* loadMissDB-copt: rm `resp.bits.firstHit` add `s2_first_hit`

* difftest: update

* yml: update the git workflow

* submodules: fix the binding commit-id of personal fork rep

* fix: github workflow add NOOP_HOME

because in constantin.scala use the absolute path of workdir by environment variable `NOOP_HOME`

* top-down: add rob head type into consideration

* top-down: put counters into EnableTopDown scope

* code opt: optimize duplicate codes

* code opt: fix index

* code opt: add more comments for readability

* code opt: add comments

* code opt: fix comments

* cachedup: code opt for readability

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

* lq: change replay cycle

* lq: change replay cycle
* change cycle to 11 36 10 10

* Revert "lq: change replay cycle"

This reverts commit 3ca74b63.
And change replay cycles

* lq: change replay cycle according to dramsim

* change Reselectlen to 7
* change replay cycle to (11, 18, 127, 17) to fit refill delay (14, 36,
188)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 32, 51)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 126, 95)

* lq: fix replay ptr update logic

* fix priority of updating ptr
* revert block_cycles_cache

* lq: change tlb replay cycle

* change tlbReplayDelayCycleCtrl to (15, 0, 126, 0)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

* huancun: version change

* util: update to main

* SimTop: delete unused comment

* constantin: fix bug which reduced emputy map

* code opt: add write api in FileRegisters

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.

This will reduce the number of replays of the load instruction which cannot
enter the missqueue

* MMU: Add sector tlb for larger capacity

* MMU: Update difftest for sector tlb

This commit aims to fix dcache plru access logic

In the previous version, when a cacheline not in l1 is accessed, a replace way
is picked and used to update l1 plru (set the way as lru). However, if the same
missed cacheline is accessed multiple times before l1 refill, l1 will pick a new
replace way and use it to update plru for each time the missed cacheline is
accessed. It makes the plru totally a mess.

To fix that problem, extra condition check is added for a missed load plru
update. Now plru is updated on:

* load/store hit (touch hit way)
* load/store primary miss (touch replacement way)
* load/store secondary miss (touch replacement way)

`updateReplaceOn2ndmiss` is enabled. Disable it if the timing is bad.

* Revert "ftq: fix unintended commitStateQueue left out (#1920)"

This reverts commit 948933da.

* Revert "break ifuwbptr dependency"

This reverts commit 2448f137.

* ftq: revert #1875, #1920

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* bump difftest, assign empty value to OBJCACHE

* local-ci: mkdir for wave/perf at run-mode

Usage:
1. run ci test
`python3 scripts/local_ci.py --xs-path $(pwd) --run`

2. print ci test name
`python3 scripts/local_ci.py --xs-path $(pwd) --show-test`

3. print ci test command into splited sh files. Run the sh manualy.
`python3 scripts/local_ci.py --xs-path $(pwd)`
More Params:
  --sh-path: default is xs-path/ci-sh.

Other Params:
  --pick-test MC: only run 'EMU - MC'
  --numa: use numa ctrl, require eypc
  --head-sha: magic word, default is today's date
  --nemu-home/--am-home: don't know if it is used

* bump utility and difftest

Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

Besides adding load/store arch database, this PR also fixed a bug which caused
prefetch using l1 info failed to work.

Former RTL change break `isFirstIssue` flag gen logic, which caused prefetcher
failed to receive prefetch train info from L1. This commit should fix that.

* ROB: add inst db drop

globalID signal output is still duplicated

* TLB: TLB will carry mem idx when req and resp

* InstDB: update the TLBFirstIssue

* InstDB: the first version is complete

* InstDB: update decode logic

* InstDB: update ctrlBlock writeback

* Merge: fix bug

* merge: fix compile bug

* code rule: rename debug signals and add db's FPGA signal control

* code rule: update db's FPGA signal control

* ldu: fix isFirstIssue flag for ldflow from rs

* ldu: isFirstIssue flag for hw pf is always false

---------
Co-authored-by: Ngood-circle <fenghaoyuan19@mails.ucas.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* test: add example to genenrate verilog for a small module

Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop

* test: add DecodeUnitTest as an example for xs' chiseltest

* ctrlblock: <> usage has changed, unidirection should use :=

* bump huancun

* makefile: mv new makefile cmd into Makefile.test

Here is a bug cause by EnableUncacheWriteOutstanding:
The case is extintr in Nexus-AM.
Three steps of the test:
  clear intrGen's intr: Stop pass interrupt. A mmio write.
  clear plic claim: complete intr. A mmio write.
  read plic claim to check: claim should be 0. A mmio read.
The corner case:
  intrGen's mmio write is to slow. The instruction after it executes
and plic claim's mmio's write & read execute before it. On the side of
core with plic, claim is cleared. But on the side of intrGen with plic,
the source of interrupt is still enabled and trigger interrupt.
So the "read plic claim to check" get a valid claim and failed.

SimTop: add support for Constantin

dtlb: set pf-tlb's ready to be True by default

sms,ldu,dcache: prefetch to l1 framework & new load flow arb

Software prefetch flow (from storeprefetch uop) will not be replayed
unless tlb reports a miss. In that case, software prefetch flow behaves
like an normal tlb missed load.

Hardware prefetch flow will never be replayed.

This commit refactors ldu load_s0 load flow arbitor logic.

Now there are 6 load flow sources, which are (priority high -> low):

src0: load replayed by LSQ (io.lsqOut)
src1: hardware prefetch from prefetchor (high confidence) (io.prefetch)
src2: int read / software prefetch first issue from RS (io.in)
src3: vec read first issue from RS (TODO)
src4: load try pointchaising when no issued or replayed load (io.fastpath)
src5: hardware prefetch from prefetchor (high confidence) (io.prefetch)

Co-authored-by: NZhangZifei <1773908404@qq.com>