- 19 11月, 2022 1 次提交
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由 William Wang 提交于
It will remove fanout from mem_release.valid releated logic
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- 18 11月, 2022 3 次提交
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由 zhanglinjuan 提交于
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由 happy-lx 提交于
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由 zhanglinjuan 提交于
* MainPipe: reduce fanout by duplicating registers * MainPipe: fix wrong assert Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 17 8月, 2022 1 次提交
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由 zhanglinjuan 提交于
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- 26 7月, 2022 1 次提交
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由 William Wang 提交于
Now we use tag_write_intend to generate ready signal for load issue It should remove the critical path from dcacheReq.ready to rs
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- 06 7月, 2022 1 次提交
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由 William Wang 提交于
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- 28 6月, 2022 1 次提交
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由 William Wang 提交于
This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing. Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load writeback to ROB. Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext. * dcache: repipeline ecc check logic for timing * chore: fix normal loadAccessFault logic * wbu: delay load unit wb for 1 cycle * dcache: add 1 extra cycle for beu error report
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- 27 6月, 2022 1 次提交
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由 zhanglinjuan 提交于
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- 06 5月, 2022 1 次提交
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由 William Wang 提交于
* chore: remove sc too many fail assertion * chore: use XSWarn()
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- 05 5月, 2022 1 次提交
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由 William Wang 提交于
s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0 for the same req
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- 28 2月, 2022 1 次提交
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由 William Wang 提交于
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- 13 1月, 2022 1 次提交
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由 zhanglinjuan 提交于
* dcache: fix bug that a block could be released twice * MainPipe: fix bug in way_en of miss_req * MainPipe: fix bug
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- 07 1月, 2022 1 次提交
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由 William Wang 提交于
ecc tag error should not be reported if we do not read tag
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- 01 1月, 2022 1 次提交
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由 William Wang 提交于
* mem: fix error csr update * dcache: l2 error will now trigger atom error * chore: fix cache error debug decoder * mem: split L1CacheErrorInfo and L1BusErrorUnitInfo
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- 28 12月, 2021 1 次提交
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由 William Wang 提交于
* dcache: add source info in L1CacheErrorInfo * ICache: fix valid signal and add source/opType * dcache: fix bug in ecc error * mem,csr: send full L1CacheErrorInfo to CSR * icache: provide cache error info for CSR * dcache: force resp hit if tag ecc error happens * mem: reorg l1 cache error report path Now dcache tag error will force trigger a hit * dcache: fix readline ecc check error * dcache: mainpipe will not be influenced by tag error * dcache: fix data ecc check error * dcache: if coh state is Nothing, do not raise error Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
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- 24 12月, 2021 1 次提交
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由 William Wang 提交于
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- 21 12月, 2021 1 次提交
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由 William Wang 提交于
* dcache: use sram to build ecc array * MainPipe: latch s1_encTag to last until s1_fire Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
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- 20 12月, 2021 3 次提交
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由 William Wang 提交于
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由 Li Qianruo 提交于
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由 William Wang 提交于
* dcache: let ecc error and l2 corrupt raise load af If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt will not raise any exception. * mem: enable cache error by default * mem: support store ecc check, add ecc error csr Support store / atom ecc check (early version) Add ecc error csr to distingush ecc error and other access fault Timing opt and unit tests to be added.
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- 14 12月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 13 12月, 2021 1 次提交
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由 zhanglinjuan 提交于
* MissQueue: loose merging condition to ease timing stress * MissQueue: remove grant_beats * MissQueue: compare block addr, not the whole addr bits * dcache: optimize timing for generating ready to sbuffer Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 10 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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- 08 12月, 2021 1 次提交
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由 William Wang 提交于
* dcache: give probe the highest priority * dcache: fix block probe logic * dcache: give replace_req higher priority
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- 01 12月, 2021 1 次提交
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由 William Wang 提交于
* sbuffer: do flush correctly while draining sbuffer * ci: enable ci for timing-memblock branch * mem: disable EnableFastForward for timing reasons * sbuffer: optimize forward mask gen timing * dcache: block main pipe req if refill req is valid Refill req comes from refill arbiter. There is not time left for index conflict check. Now we simplily block all main pipe req when refill req comes from miss queue. * dcache: delay some resp signals for better timing * dcache: optimize wbq enq entry select timing * WritebackQueue: optimize enqueue logic fir timing * WritebackQueue: always reject a req when wbq is full * Revert "ci: enable ci for timing-memblock branch" This reverts commit 32453dc4. * WritebackQueue: fix bug in secondary_valid Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
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- 29 11月, 2021 2 次提交
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由 zhanglinjuan 提交于
* dcache: merge replace pipe with main pipe for timing reason * MainPipe: fix bug in s3_fire * MainPipe: fix bug in delay_release sent to wbq * MainPipe: fix bug in blocking policy * MainPipe: send io.replace_resp in stage 3 * MainPipe: fix bug in miss_id sent to wbq * MainPipe: fix bug Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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由 William Wang 提交于
* sbuffer: do flush correctly while draining sbuffer * mem: disable EnableFastForward for timing reasons * sbuffer: optimize forward mask gen timing * dcache: block main pipe req if refill req is valid Refill req comes from refill arbiter. There is not time left for index conflict check. Now we block all main pipe req when refill req comes from miss queue. * dcache: delay some resp signals for better timing * dcache: optimize wbq enq entry select timing * dcache: decouple missq req.valid to valid & cancel * valid is fast, it is used to select which miss req will be sent to miss queue * cancel can be slow to generate, it will cancel miss queue req in the last moment * sbuffer: optimize noSameBlockInflight check timing
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- 16 11月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 15 11月, 2021 2 次提交
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由 wakafa 提交于
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由 William Wang 提交于
DCache timing problem has not been solved yet. DCache structure will be further changed. * sbuffer: add extra perf counters * sbuffer: optmize timeout replay check timing * sbuffer: optmize do_uarch_drain check timing Now we only compare merge entry's vtag, check will not start until mergeIdx is generated by PriorityEncoder * mem, lq: optmize writeback select logic timing * dcache: replace missqueue reill req arbiter * dcache: refactor missqueue entry select logic * mem: add comments for lsq data * dcache: give amo alu an extra cycle * sbuffer: optmize sbuffer forward data read timing
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- 04 11月, 2021 1 次提交
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由 William Wang 提交于
* dcache: do not check readline rmask This should opt bank_conflict check timing * dcache: block replace if store s1 valid It takes quite long to generate way_en in mainpipe s1. As a result, use s1 way_en to judge if replace should be blocked will cause severe timing problem Now we simply block replace if mainpipe.s1.valid Refill timing to be optmized later * sbuffer: delay sbuffer enqueue for 1 cycle With store queue growing larger, read data from datamodule nearly costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle for better timing. * dcache: reduce probe queue size * dcache: replace probe pipe req RRArbiter with Arbiter * dcache: reduce writeback queue size for timing opt * dcache: delay wbqueue enqueue req for 1 cycle Addr enqueue req will compare its addr with addrs in all writeback entries to check if it should be blocked. Delay enqueue req will give that process more time. * dcache: set default replacer to setplru It does not change current design * dcache: fix wbqueue req_delayed deadlock We delayed writeback queue enq for 1 cycle, missQ req does not depend on wbQ enqueue. As a result, missQ req may be blocked in req_delayed. When grant comes, that req should also be updated * dcache: remove outdated require * dcache: replace missReqArb RRArbiter with Arbiter * perf: add detailed histogram for low dcache latency * dcache: fix wbqueue entry alloc logic * dcache: opt probe req timing In current design, resv_set is maintained in dcache. All probe req will be blocked if that addr is in resv_set. However, checking if that addr is in resv_set costs almost half a cycle, which causes severe timing problem. Now when we update update_resv_set, all probe reqs will be blocked in the next cycle. It should give Probe reservation set addr compare an independent cycle, which will lead to better timing
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- 23 10月, 2021 1 次提交
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由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
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- 20 10月, 2021 1 次提交
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由 zhanglinjuan 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * IFU: add performance counters and mmio af * icache replacement policy moniter * ifu miss situation moniter * icache miss rate * raise access fault when found mmio req * Add framework for seperated main pipe and reg meta array * Rewrite miss queue for seperated pipes * Add RefillPipe * chore: rename NewSbuffer.scala * cache: add CacheInstruction opcode and reg list * CSR: add cache control registers * Add Replace Pipe * CacheInstruction: add CSRs for cache instruction * mem: remove store replay unit * Perf counter to be added * Timing opt to be done * mem: update sbuffer to support new dcache * sbuffer: fix missqueue time out logic * Merge remote-tracking branch 'origin/master' into dcache-rm-sru * chore: fix merge conflict, remove nStoreReplayEntries * Temporarily disable TLMonitor * Bump huancun (L2/L3 MSHR bug fix) * Rewrite main pipe * ReplacePipe: read meta to decide whether data should be read * RefillPipe: add a store resp port * MissQueue: new req should be rejected according to set+way * Add replacement policy interface * sbuffer: give missq replay the highest priority Now we give missqReplayHasTimeOut the highest priority, as eviction has already happened Besides, it will fix the problem that fix dcache eviction generate logic gives the wrong sbuffer id * Finish DCache framework * Split meta & tag and use regs to build meta array * sbuffer: use new dcache io * dcache: update dcache resp in memblock and fake d$ * Add atomics processing flow * Refactor Top * Bump huancun * DCacheWrapper: disable ld fast wakeup only when bank conflict * sbuffer: update dcache_resp difftest io * MainPipe: fix combinational loop * Sbuffer: fix bug in assert * RefillPipe: fix bug of getting tag from addr * dcache: ~0.U should restrict bit-width * LoadPipe: fix bug in assert * ReplacePipe: addr to be replaced should be block-aligned * MainPipe: fix bug in required coh sending to miss queue * DCacheWrapper: tag write in refill pipe should always be ready * MainPipe: use replacement way_en when the req is from miss queue * MissQueue: refill data should be passed on to main pipe * MainPipe: do not use replacement way when tag match * CSR: clean up cache op regs * chore: remove outdated comments * ReplacePipe: fix stupid bug * dcache: replace checkOneHot with assert * alu: fix bug of rev8 & orc.b instruction * MissQueue: fix bug in the condition of mshr accepting a req * MissQueue: add perf counters * chore: delete out-dated code * chore: add license * WritebackQueue: distinguish id from miss queue * AsynchronousMetaArray: fix bug * Sbuffer: fix difftest io * DCacheWrapper: duplicate one more tag copy for main pipe * Add perf cnt to verify whether replacing is too early * dcache: Release needs to wait for refill pipe * WritebackQueue: fix accept condition * MissQueue: remove unnecessary assert * difftest: let refill check ingore illegal mem access * Parameters: enlarge WritebackQueue to break dead-lock * DCacheWrapper: store hit wirte should not be interrupted by refill * Config: set nReleaseEntries to twice of nMissEntries * DCacheWrapper: main pipe read should block refill pipe by set Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NLinJiawei <linjiav@outlook.com> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NJinYue <jinyue20s@ict.ac.cn> Co-authored-by:
Zhangfw <471348957@qq.com>
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- 28 9月, 2021 1 次提交
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由 Yinan Xu 提交于
* rename Roq to Rob * remove trailing whitespaces * remove unused parameters
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- 27 9月, 2021 2 次提交
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由 wakafa 提交于
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由 Jiawei Lin 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * dcache: fix l1 probe index generate logic * Now right probe index will be used according to the len of alias bits * dcache: clean up amo pipeline * DCacheParameter rowBits will be removed in the future, now we set it to 128 to make dcache work * dcache: fix amo word index * bump huancun Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 25 8月, 2021 1 次提交
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由 Jiawei Lin 提交于
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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