* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
  in order to remove casting operation in composer

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* reduce number of tables to 4, meanwhile quadrupling number of entries per table, improving area efficiency
* use per bank wrbypass
* invalidate read response when writing to SRAM
* move validArray and useful bit into SRAMs, thus reducing area
* use an optimized history config for such table sizes

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

* let tage SRAM writes cover reads, ignoring read data
* let wrbypass to be 16 entries

* use a single bit for each entry and adopt the reset mechanism introduced in TAGE-SC-L
* use regfile instead of SRAMs to store u bits

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

* use compressed info to do redirects
* implement folded history class

previously we may use random data from ftq meta sram, and now we fixed this issue

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

* modify UBitPeriod to one-eights of the previous value to adapt
  to nRows enlarged by eight times
* fix a bug assigning sc update mask