ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles

* FtqToICache add bypass write signal and use bypass signal

* IFU: ignore ICache access bundle

* ICacheMainPipe: expand meta/data access output to 4 identical vector
output, each output is connected to a copied register trigger by FTQ
requests

* IPrefetch/ReplacePipe: expand meta/data access outpu to 4 indentical
vector output, and each output is triggered by the same signal group

* add ICachPartWayArray to wrap a part-way module

* SRAM array array_0 array_1: width × 1/4 and depth stay unchanged

* separate ifu req and icache req for timing optimization

* both ifu ftq_req_ready and icache ftq_req_ready depend on each other

* ifu and icache has pc_mem register

[WIP]ICacheMainPipe: add copied registers

[WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied

[WIP] FTQ:  delete outside bypass

* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq

* ctrl: add data modules for pc and jalr_target

This commit adds two data modules for pc and jalr_target respectively.
They are the same as data modules in frontend. Should benefit timing.

* jump: reduce pc and jalr_target read latency

* ftq: add predecode redirect update target interface, valid only on ifuRedirect

* ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>

and remove all bypass for ftq_pc_mem

* without s2_valid, invalid pmp_af will cause wait_state turn into
wait_pmp_except and incorrect read data

- Move tag and idx compare to s1 in secondary miss

- Delay 1 cycle when PMP report an access fault and ICache miss

using RegNext causes a memory fetch req incorrectly perceived as a mmio
req

and improve parameterizaton of fromMicroBTBEntry

This reverts commit 99529e48.

This reverts commit 33b74280.

- Move tag and idx compare to s1 in secondary miss

- Delay 1 cycle when PMP report an access fault and ICache miss

using RegNext causes a memory fetch req incorrectly perceived as a mmio
req

* add one cycle stall to ftb miss update, and
* add one cycle delay to all other predictors

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* IFU <bug-fix>: deal with itlb miss for resend

* IFU <bug fix>: enable crossPageFault for resend-pf
Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of `valid`

* config: minimalconfig use non-inclusive L3 cache

* config: make simulation config dependent on FPGAPlatform

* axi4,mem: fix typo for pending_write_resp_id

* axi4,mem: fix has_write_resp condition

Usage:

When make emu, please use EMU_TRACE=1, EMU_TRACE=vcd or EMU_TRACE=VCD
to dump waveform of vcd format, and use EMU_TRACE=fst or EMU_TRACE=FST
to dump waveform of fst format.

When use xiangshan.py, please add --trace to dump waveform of vcd format,
and add --trace-fst to dump waveform of fst format.