- 01 4月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 31 3月, 2021 5 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters * csr: bug fixing for perf-cnt wiring
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Jay 提交于
* AXIFlash: use blackbox to rebuild flash * device.cpp: add init_flash * Add flash.cpp for DPI-C funtion * Flash: use USE_BIN to enable FI from flash * AXIFlash: delete original flash
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- 30 3月, 2021 5 次提交
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 wakafa 提交于
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由 zhanglinjuan 提交于
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由 Yinan Xu 提交于
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- 29 3月, 2021 1 次提交
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由 wakafa 提交于
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- 28 3月, 2021 1 次提交
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由 allen 提交于
* Fixed perf counter does not print bug in BlockInclusiveCache. * Bump l2 Co-authored-by: NLinJiawei <linjiav@outlook.com>
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- 27 3月, 2021 1 次提交
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由 ljw 提交于
* L2/L3: set replacement policy to plru * Bump l2
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- 26 3月, 2021 7 次提交
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由 Yinan Xu 提交于
L1/L2 Add perf counters
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由 Allen 提交于
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由 Allen 提交于
L2 and L3 Only enablePerf when XSCore enables perf.
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由 Allen 提交于
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由 Wonicon 提交于
* l2,timing: bump l2/l3 cache This will necessarily add several cycles to L2/L3 cache responsing time. * l2,l3: bump timing tweaks Resolved timeout in debian boot. Remove repeat feature to avoid directory disturbing (repeat allows to use previous tag and victim info which is dangerous). TODO: - [ ] Another directory atomicity weakness that heavy l1 release can overwrite l3tol2 probe directory update, for example: l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback l2.probeAck.BtoB write non-dirty (not saved) l3 think l2 is branch, but l2 is still trunk. But forbid nestB and nestC can cause deadlock... - [ ] Delay bankedStore one more cycle for L3 large sram timing. * l2,l3: change mshr amount to 15
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由 Lemover 提交于
* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue * RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue
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- 25 3月, 2021 5 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 Allen 提交于
Not tested yet. Added: * L1 MSHR occupation * L1 MSHR latency * L1 Load Miss latency * L1 Store latency * L1 Store occupation * L1 Load req count
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由 Allen 提交于
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由 Allen 提交于
Now we can put a performance value into several bins and count them. In this way, we can get a distribution of this performance value.
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers * Ftq: bypass 'commit state' to fix dequeue bug * perf: uptimize perf-cnt in ctrlblock & ftq * perf: fix compilation problem in ftq * perf: remove duplicate perf-cnt * perf: calcu extra walk cycle exceeding frontend flush bubble * Revert "perf: calcu extra walk cycle exceeding frontend flush bubble" This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70. * perf: add perf-cnt for ifu * perf: add perf-cnt for rs * RS: optimize numExist signal * RS: fix some typo * perf: add QueuePerf util to monitor usage info of queues * perf: remove some duprecate perfcnt
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- 24 3月, 2021 3 次提交
- 23 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 22 3月, 2021 8 次提交
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由 Yinan Xu 提交于
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由 ljw 提交于
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由 Yinan Xu 提交于
Update SoC and emu configurations
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
Add bus error unit and connect ecc errors to beu
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由 zhanglinjuan 提交于
* MissQueue: add perf cnt for inflight entries in maximum * MissQueue: max_inflight ignores cycles when missQueue is empty
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由 Lemover 提交于
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- 21 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 20 3月, 2021 1 次提交
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由 Yinan Xu 提交于
This allows the software to determine whether an address can be read or written.
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