- target -> nextStartAddr
- nextlineStart = cachelineAlign(startAddr) + 64

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

This commit changes the condition to update mtval and stval.

According to the RISC-V spec, when a trap is taken into M/S-mode,
mtval/stval is either set to zero or written wrih exception-specific
information to assist software in handling the trap.

Previously in XiangShan, mtval/stval is updated depending on the
current priviledge mode, which is incorrect.

* MissQueue: loose merging condition to ease timing stress

* MissQueue: remove grant_beats

* MissQueue: compare block addr, not the whole addr bits

* dcache: optimize timing for generating ready to sbuffer
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: fix write mask for mstatus, mepc and sepc

This commit fixes the write mask for mstatus, mepc and sepc.

According to the RISC-V instruction manual, for RV64 systems,
the SXL and UXL fields are WARL fields that control the value of
XLEN for S-mode and U-mode, respectively. For RV64 systems, if
S-mode is not supported, then SXL is hardwired to zero. For RV64
systems, if U-mode is not supported, then UXL is hardwired to zero.

Besides, mepc[0] and sepc[0] should be hardwired to zero.

* wb,load: delay load fp for one cycle

* csr: add mconfigptr, but hardwire to 0 now

* bump huancun

* csr: add *BE to mstatusStruct which are hardwired to 0

* Remove unused files

* csr: fix bug of xret clear mprv

* bump difftest

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

* mem,atomics: delay exception info for one cycle

* SoC: insert more buffers into mmio path

* SoC: insert buffer between l3_xbar and l3_banked_xbar

* Optimze l3->ddr path

* Bump huancun
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

* L2/L3: fix prefetch train address

* HuanCun: update SRAMTemplate

* Config: Keep the client dir capacity of L3 twice the L2

* Bump huancun

Soft prefetch will be always marked as "load hit"

All bits for stvec and mtvec are writable in XiangShan.

According to the RISC-V spec, {m,s}tvec[1:0] are MODE bits. When
MODE=Vectored, all synchronous exceptions into M/S mode cause the pc
to be set to the address in the BASE field, whereas interrupts cause
the pc to be set to the address in the BASE field plus four times
the interrupt cause number.

If XiangShan decides to not support vectored mode, {m,s}tvec[1:0]
should be hardwired to zero.

According to RISC-V spec, for the JALR instruction, its target address
is obtained by adding the sign-extended 12-bit I-immediate to the
register rs1, then setting the least-significant bit of the result
to zero.

* TLB: when miss, regnext the req sent to ptw

* PTWFilter: timing optimzation of do_iss that ignore ptwResp's filter

* StoreUnit: logic optimization of from s2_mmio to s2_out_valid

* ptwfilter: when issue but filtered, clear the v bit

special case that
ptw.resp clear all the duplicate req when arrive to filter
ptw_resp is the RegNext of ptw.resp and it filters ptw.req
when ptw_resp filter the req but ptw.resp not filter the tlb_req to
stop do_enq, then the v bit of the req will not be cleared ever.

It will be more correct to fliter the entries and tlb_req with ptw_resp,
but the timing restriction says no. So just use the confusing trick
to slove the complicate corner case.

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits change, we also need
to delay the flush for two cycles. We assume branch misprediction or
memory violation does not cause csrCtrl to change.

* let tage SRAM writes cover reads, ignoring read data
* let wrbypass to be 16 entries

* mem,cacheop: fix read data writeback

* mem,cacheop: rename cacheop state bits

These bits are different from w_*, s_* bits in cache

* mem: enable icache op feedback

* icache: update cache op implementation

* chore: remove cache op logic from XSCore.scala

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

This commit adds WritebackSink and WritebackSource parameters for
multiple modules. These traits hide implementation details from
other modules by defining IO-related functions in modules.

By using WritebackSink, ROB is able to choose the writeback sources.
Now fflags and exceptions are connected from exe units to reduce write
ports and optimize timing.

Further optimizations on write-back to RS and better coding style to
be added later.

* csr.satp: add r/w mask of ppn part

* ci: add unit test, satp should concern PADDRBITS

* csr.xstatus: XS field is ready-only

* bump ready-to-run

* bump ready-to-run, update nemu so

* fix typo

Now we RegNext(refill_req) for 1 cycle. It will provide more
time for refillShouldBeBlocked calcuation

* dcache: give probe the highest priority

* dcache: fix block probe logic

* dcache: give replace_req higher priority

* mem,cacheop: fix read data writeback

* mem,cacheop: rename cacheop state bits

These bits are different from w_*, s_* bits in cache