- 08 2月, 2023 1 次提交
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由 William Wang 提交于
sms,ldu,dcache: prefetch to l1 framework & new load flow arb
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- 06 2月, 2023 3 次提交
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由 wakafa 提交于
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由 bugGenerator 提交于
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由 William Wang 提交于
Software prefetch flow (from storeprefetch uop) will not be replayed unless tlb reports a miss. In that case, software prefetch flow behaves like an normal tlb missed load. Hardware prefetch flow will never be replayed.
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- 05 2月, 2023 5 次提交
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由 William Wang 提交于
This commit refactors ldu load_s0 load flow arbitor logic. Now there are 6 load flow sources, which are (priority high -> low): src0: load replayed by LSQ (io.lsqOut) src1: hardware prefetch from prefetchor (high confidence) (io.prefetch) src2: int read / software prefetch first issue from RS (io.in) src3: vec read first issue from RS (TODO) src4: load try pointchaising when no issued or replayed load (io.fastpath) src5: hardware prefetch from prefetchor (high confidence) (io.prefetch)
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由 xiwenx 提交于
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由 czw 提交于
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由 Haoyuan Feng 提交于
Co-authored-by: NZhangZifei <1773908404@qq.com>
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由 Haoyuan Feng 提交于
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- 04 2月, 2023 1 次提交
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由 Steve Gou 提交于
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- 02 2月, 2023 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 01 2月, 2023 4 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 31 1月, 2023 2 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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- 30 1月, 2023 3 次提交
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由 William Wang 提交于
TODO: ldflow from prefetch to be added to ldflow select logic
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由 William Wang 提交于
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由 William Wang 提交于
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- 29 1月, 2023 8 次提交
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由 William Wang 提交于
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由 William Wang 提交于
Now SMS is the same as f684ed00
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
TLB and Huancun conflict fix is not included in this commit
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- 28 1月, 2023 11 次提交
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由 William Wang 提交于
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由 LinJiawei 提交于
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由 William Wang 提交于
This commit update coh check assertion to enable aggressive prefetch miss req / store miss req merge. Previous wrong assertion forbids store req from stoping a previous prefetch For example, consider 2 reqs with the same p address fire in order: 1) A prefetch with alias bit 00 need to change coh state from N->T 2) A store with alias bit 11 need to change coh state from B->T Then prefetch and store miss req will be merged in the same missq entry. Store req (2) should be able to stop prefetch (1) so that a ping-pong process will not start
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 LinJiawei 提交于
Note that Huancun have not been updated in this commit
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 William Wang 提交于
No extra latency introduced
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由 William Wang 提交于
Added meta_prefetch and meta_access related sim perf counter For now, optional dcache meta prefetch and access can be removed safely
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由 William Wang 提交于
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