* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

* FrontendBundle.scala: change IFU-to-Ftq Bundle defination.
    delete jump and branch, instead use missOffset and cfiOffset.
* ICache.scala: fix some name error using IDEA
* IFU.scala: update bundle connection logic according to FrontendBundle
* PreDecode.scala: generate missOffset and cfiOffset

add handshake between pipeline stage

* Recover Ftq Pointer and send miss req to I$ MSHRs
* Instruction reorder is done by Ftq

* TODO: need a solution for fetch-on-miss

* ftq: only when corresponding write back port is valid can cfiIndex_vec be updated

* ftq: fix a bug updating cfiInfo when multiple wb ports target the same ftqEntry

added arbitration logic on this situation
now we select the write back request with the smallest ftq offset

* Only ssip in sip is writeable in smode
* Add sip write permission check
* Fix mipReg write logic

In this commit, we add License for XiangShan project. 

* backend,RS: add numEnq parameter to allow multiple enqueue instructions

* backend,RS: support multiple issue instructions at each cycle

* Update mill and rocket-chip

* [WIP] auto generate dts by diplomacy

* PTW: fix typo

* PTW: add perf for req's count & cycle

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite ptw for multi req support

* PTW: remove some assert, fix level init bug

* PTW: itlb has highter priority than dtlb

* PTW: fix bug that mix cache's resp logic

* PTW: fix stupid bug that mix .U and .W

* PTW: replay will not be blocked if fsm empty

* PTW: miss queue req may return miss queue

In the before design, only miss queue req can go into
fsm, and would not be blocked.
Now, to simplify design, miss queue req are just the
same with new req, may blocked, going to fsm or miss queue.

* PTW: fix ptw filter iss valid bug

* PTW.fsm: fix bug that should not mem.req when sfenceLatch

* PTW: fix ptw sfenceLatch's bug

* PTW: add some perf counters

* PTW: fix bug in filter enq ptr logic

* PTW: fix bug of sfence in ptw

* test: add current branch to ci-test, tmp

* PTW: fix bug of cache's hit logic and fsm's pf

* PTW: fix bug of filter's enq and block* signal

* PTW: fix bug of filter's pteResp filter

* PTW: add some assert of filter's counter

* PTW: fix bug of filter's enq logic

* PTW: set PTWMSHRSIZE 16

* PTW: fix naive perf counter's bug

* PTW: set PTWMSHRSIZE 8

* PTW: set PTWMSHRSIZE 32

* Revert "PTW: set PTWMSHRSIZE 32"

This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.

* Revert "test: add current branch to ci-test, tmp"

This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls