* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

* use a single bit for each entry and adopt the reset mechanism introduced in TAGE-SC-L
* use regfile instead of SRAMs to store u bits

* let the hit signal of each stage be used at last

* use one hot muxes for ftb read resp
* generate branch history shift one hot vec for history update src sel
  and update for all possible shift values

This commit optimizes instruction fusion detection logic for fused
addw{byte, bit, zexth, sexth}, mulw7, and logic{lsb, zexth}
instructions.

Previously we use fuType and fuOpType from the normal decoder, and this
incurs a bad timing. Now we change the detection logic to use only the
raw instructions. Though the fused instruction still uses the
fuOpType from the normal decoder, there should be only serveral MUXes
left.

ftq: optimize ifu request timing

update hpmevent defalt value and write mask; modify fetch trigger res…

This commit changes how isFreed is calculated. Instead of using
refCounter in the next, we compute it at this cycle and RegNext it.

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

ftq: code clean ups

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a
"speculatively assigned" sqIdx, as it is hard to track store insts in
dispatch queue. Yet we can still use "speculatively assigned" robIdx
for memory dependency predictor.

For now, memory dependency predictor uses "speculatively assigned"
robIdx to track inflight store.

However, sqIdx is still used to track those store which's addr is valid
but data it not valid. When load insts try to get forward data from
those store, load insts will get that store's sqIdx and wait in RS.
They will not waken until store data with that sqIdx is issued.

* mdp: add track robIdx recover logic

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

bpu: extract wrbypass to be a module

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

BPU: Change the u in the ITTAGE from register to SRAM implementation

This bug happens when a branch prediction results in a fetch to MMIO space, and the backend flush could not flush the MMIO, thus results in blocking.

DCache timing problem has not been solved yet. DCache structure will be further changed.

* sbuffer: add extra perf counters

* sbuffer: optmize timeout replay check timing

* sbuffer: optmize do_uarch_drain check timing

Now we only compare merge entry's vtag, check will not start until
mergeIdx is generated by PriorityEncoder

* mem, lq: optmize writeback select logic timing

* dcache: replace missqueue reill req arbiter

* dcache: refactor missqueue entry select logic

* mem: add comments for lsq data

* dcache: give amo alu an extra cycle

* sbuffer: optmize sbuffer forward data read timing

* Untested Trigger Implementation
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>