* ras: partly handle stack overflow problems

* ras: add overflow and underflow statistics

useRefillReg is not be used when holdRead

FDivSqrt: update to srt4

Bump chisel to v3.4.3 and re-add `-X verilog` parameter for chisel runs.
Our transform seems to have conflicts when `-X verilog` is not set.

* Fixed perf counter does not print bug in BlockInclusiveCache.

* BlockInclusiveCache: Dont Probe L1 On Hint Hit.

* L2 use UncachedGet, L3 cache Get.

* Bump L2
Co-authored-by: NLinJiawei <linjiav@outlook.com>

* Add ResetRegGen module to generate reset signals for different modules

To meet physical design requirements, reset signals for different modules
need to be generated respectively. This commit adds a ResetRegGen module
to automatically generate reset registers and connects different reset
signals to different modules, including l3cache, l2cache, core.
L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are
reset one by one.

* ICache: set holdRead to true for meta and data SRAMs

SyncReadMem generates the verilog behavior model whose output rdata is always
mem(RegNext(raddr)). Accidentally, ICache will not change meta and data
SRAMs' raddr if the second pipeline stage is stalled (and ren is false).
Thus, the SRAMs seem to have the holdRead property.
Obviously, it will cause errors on real SRAMs. We set holdRead to true to fix the bug.

* L1plusCache: set holdRead to true for SRAMs

* Makefile: enable SRAM randomization for verilator simulation

Previously we don't use the --infer-rw and --repl-seq-mem flags for simulation verilog.
However, the SyncReadMem fails to generate random read data when ren is not set.
In this commit, SyncReadMem is changed to blackboxes and generated by the vlsi_mem_gen script.
RANDOMIZE_GARBAGE_ASSIGN flag is defined to enable randomization.

SyncReadMem generates the verilog behavior model whose output rdata is always
mem(RegNext(raddr)). Accidentally, ICache will not change meta and data
SRAMs' raddr if the second pipeline stage is stalled (and ren is false).
Thus, the SRAMs seem to have the holdRead property.
Obviously, it will cause errors on real SRAMs. We set holdRead to true to fix the bug.

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

* csr: bug fixing for perf-cnt wiring

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

* AXIFlash: use blackbox to rebuild flash

* device.cpp: add init_flash

* Add flash.cpp for DPI-C funtion

* Flash: use USE_BIN to enable FI from flash

* AXIFlash: delete original flash

* Fixed perf counter does not print bug in BlockInclusiveCache.

* Bump l2
Co-authored-by: NLinJiawei <linjiav@outlook.com>

* L2/L3: set replacement policy to plru

* Bump l2

L1/L2 Add perf counters

Previously in commit 298aa395,
we incorrectly set simulation freq to 1,000,000.

L2 and L3 Only enablePerf when XSCore enables perf.

* l2,timing: bump l2/l3 cache

This will necessarily add several cycles to L2/L3 cache responsing time.

* l2,l3: bump timing tweaks

Resolved timeout in debian boot.
Remove repeat feature to avoid directory disturbing
(repeat allows to use previous tag and victim info which is dangerous).

TODO:
- [ ] Another directory atomicity weakness that heavy l1 release can
      overwrite l3tol2 probe directory update, for example:
      l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback
               l2.probeAck.BtoB write non-dirty (not saved)
      l3 think l2 is branch, but l2 is still trunk.
      But forbid nestB and nestC can cause deadlock...
- [ ] Delay bankedStore one more cycle for L3 large sram timing.

* l2,l3: change mshr amount to 15

* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue

* RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue

XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

Not tested yet.

Added:
* L1 MSHR occupation
* L1 MSHR latency
* L1 Load Miss latency
* L1 Store latency
* L1 Store occupation
* L1 Load req count