- 21 1月, 2021 7 次提交
- 20 1月, 2021 14 次提交
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Yinan Xu 提交于
Icache add mmio support for flash instruction fetch
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由 Yinan Xu 提交于
backend: bug fixes for exception-related logic in Roq and CSR
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 jinyue110 提交于
icache: add not bus-width aligned MMIO req support IFU: add mmio aligned function
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由 Fa_wang 提交于
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由 jinyue110 提交于
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由 Yinan Xu 提交于
If we DontCare a register write data, chisel will convert it to 0 (or somthing else?). Thus, for exceptionVec, we cannot simply DontCare the wdata. Instead, we have to assign them separately.
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由 ljw 提交于
Opt fmisc timing
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由 LinJiawei 提交于
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- 19 1月, 2021 19 次提交
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由 Yinan Xu 提交于
bug fixes in TLB, PTW and sbuffer
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由 jinyue110 提交于
s2_hit use s3_valid :)
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由 jinyue110 提交于
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
LoadQueue: opt writeback select timing
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 William Wang 提交于
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由 jinyue110 提交于
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由 Yinan Xu 提交于
sbuffer: add sq empty check
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由 Yinan Xu 提交于
icache: fix ipf bug
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由 Yinan Xu 提交于
Perf: Modify predictor counter logic
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由 William Wang 提交于
When sbuffer checks if it is empty, it needs to check if sq is also empty so there is no pending store. Errors will emerge rarely if we do not check sq.
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由 jinyue110 提交于
Previously, we only give the first instrcution to backend when the packet causes a page fault. It will be stuck if not because waymask is 0 because no hit but hit includes ipf. So we seperates them.
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由 jinyue110 提交于
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由 jinyue110 提交于
exception and mmio judgement is done in tlb according to paddr. icache send mmio request to Instruction uncache module. It send TileLink GET to peripherals like flash and receive instructions per beat.
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