TLB and Huancun conflict fix is not included in this commit

This commit update coh check assertion to enable aggressive
prefetch miss req / store miss req merge. Previous wrong
assertion forbids store req from stoping a previous prefetch

For example, consider 2 reqs with the same p address fire in order:
1) A prefetch with alias bit 00 need to change coh state from N->T
2) A store with alias bit 11 need to change coh state from B->T
Then prefetch and store miss req will be merged in the same missq
entry. Store req (2) should be able to stop prefetch (1) so that a
ping-pong process will not start

Note that Huancun have not been updated in this commit

No extra latency introduced

Added meta_prefetch and meta_access related sim perf counter

For now, optional dcache meta prefetch and access can be removed safely

* L2TLB: Add L2TLB Resp Check in difftest

* L1TLB: Add L1TLB Resp Check in difftest

* L2TLB: Do not Check Resp with difftest when access fault

* Update difftest

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs
have been reorganized for that. 

The dummy predictor is disabled by default. 

Besides, dcache bank conflict check has been optimized. It may cause timing problems,
to be fixed in the future.

* ideal wpu

* BankedDataArray: change architecture to reduce bank_conflict

* BankedDataArray: add db analysis

* Merge: the rest

* BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up

* Load Logic: changed to be as expected

reading data will be delayed by one cycle to make selection
writing data will be also delayed by one cycle to do write operation

* fix: ecc check error

* update the gitignore

* WPU: add regular wpu and change the replay mechanism

* WPU: fix refill fail bug, but a new addiw fail bug appears

* WPU: temporarily turn off to PR

* WPU: tfix all bug

* loadqueue: fix the initialization of replayCarry

* bankeddataarray: fix the bug

* DCacheWrapper: fix bug

* ready-to-run: correct the version

* WayPredictor: comments clean

* BankedDataArray: fix ecc_bank bug

* Parameter: set the enable signal of wpu

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

* PTW: Fix a bug when sfence

* PTW: Fix mem_addr_update when sfence

This PR remove data in lq.

All cache miss load instructions will be replayed by lq, and the forward path to the D channel
and mshr is added to the pipeline.
Special treatment is made for uncache load. The data is no longer stored in the datamodule
but stored in a separate register. ldout is only used as uncache writeback, and only ldout0
will be used. Adjust the priority so that the replayed instruction has the highest priority in S0.

Future work:
1. fix `milc` perf loss
2. remove data from MSHRs

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

* L2TLB: Fix a bug of Prefetcher

* MMU: Add ChiselDB

* MMU: Add Fake PTW

* MMU: Fix ChiselDB for dual core