- 10 11月, 2021 1 次提交
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由 wakafa 提交于
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- 04 11月, 2021 1 次提交
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由 William Wang 提交于
* dcache: do not check readline rmask This should opt bank_conflict check timing * dcache: block replace if store s1 valid It takes quite long to generate way_en in mainpipe s1. As a result, use s1 way_en to judge if replace should be blocked will cause severe timing problem Now we simply block replace if mainpipe.s1.valid Refill timing to be optmized later * sbuffer: delay sbuffer enqueue for 1 cycle With store queue growing larger, read data from datamodule nearly costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle for better timing. * dcache: reduce probe queue size * dcache: replace probe pipe req RRArbiter with Arbiter * dcache: reduce writeback queue size for timing opt * dcache: delay wbqueue enqueue req for 1 cycle Addr enqueue req will compare its addr with addrs in all writeback entries to check if it should be blocked. Delay enqueue req will give that process more time. * dcache: set default replacer to setplru It does not change current design * dcache: fix wbqueue req_delayed deadlock We delayed writeback queue enq for 1 cycle, missQ req does not depend on wbQ enqueue. As a result, missQ req may be blocked in req_delayed. When grant comes, that req should also be updated * dcache: remove outdated require * dcache: replace missReqArb RRArbiter with Arbiter * perf: add detailed histogram for low dcache latency * dcache: fix wbqueue entry alloc logic * dcache: opt probe req timing In current design, resv_set is maintained in dcache. All probe req will be blocked if that addr is in resv_set. However, checking if that addr is in resv_set costs almost half a cycle, which causes severe timing problem. Now when we update update_resv_set, all probe reqs will be blocked in the next cycle. It should give Probe reservation set addr compare an independent cycle, which will lead to better timing
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- 23 10月, 2021 1 次提交
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由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
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- 20 10月, 2021 1 次提交
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由 zhanglinjuan 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * IFU: add performance counters and mmio af * icache replacement policy moniter * ifu miss situation moniter * icache miss rate * raise access fault when found mmio req * Add framework for seperated main pipe and reg meta array * Rewrite miss queue for seperated pipes * Add RefillPipe * chore: rename NewSbuffer.scala * cache: add CacheInstruction opcode and reg list * CSR: add cache control registers * Add Replace Pipe * CacheInstruction: add CSRs for cache instruction * mem: remove store replay unit * Perf counter to be added * Timing opt to be done * mem: update sbuffer to support new dcache * sbuffer: fix missqueue time out logic * Merge remote-tracking branch 'origin/master' into dcache-rm-sru * chore: fix merge conflict, remove nStoreReplayEntries * Temporarily disable TLMonitor * Bump huancun (L2/L3 MSHR bug fix) * Rewrite main pipe * ReplacePipe: read meta to decide whether data should be read * RefillPipe: add a store resp port * MissQueue: new req should be rejected according to set+way * Add replacement policy interface * sbuffer: give missq replay the highest priority Now we give missqReplayHasTimeOut the highest priority, as eviction has already happened Besides, it will fix the problem that fix dcache eviction generate logic gives the wrong sbuffer id * Finish DCache framework * Split meta & tag and use regs to build meta array * sbuffer: use new dcache io * dcache: update dcache resp in memblock and fake d$ * Add atomics processing flow * Refactor Top * Bump huancun * DCacheWrapper: disable ld fast wakeup only when bank conflict * sbuffer: update dcache_resp difftest io * MainPipe: fix combinational loop * Sbuffer: fix bug in assert * RefillPipe: fix bug of getting tag from addr * dcache: ~0.U should restrict bit-width * LoadPipe: fix bug in assert * ReplacePipe: addr to be replaced should be block-aligned * MainPipe: fix bug in required coh sending to miss queue * DCacheWrapper: tag write in refill pipe should always be ready * MainPipe: use replacement way_en when the req is from miss queue * MissQueue: refill data should be passed on to main pipe * MainPipe: do not use replacement way when tag match * CSR: clean up cache op regs * chore: remove outdated comments * ReplacePipe: fix stupid bug * dcache: replace checkOneHot with assert * alu: fix bug of rev8 & orc.b instruction * MissQueue: fix bug in the condition of mshr accepting a req * MissQueue: add perf counters * chore: delete out-dated code * chore: add license * WritebackQueue: distinguish id from miss queue * AsynchronousMetaArray: fix bug * Sbuffer: fix difftest io * DCacheWrapper: duplicate one more tag copy for main pipe * Add perf cnt to verify whether replacing is too early * dcache: Release needs to wait for refill pipe * WritebackQueue: fix accept condition * MissQueue: remove unnecessary assert * difftest: let refill check ingore illegal mem access * Parameters: enlarge WritebackQueue to break dead-lock * DCacheWrapper: store hit wirte should not be interrupted by refill * Config: set nReleaseEntries to twice of nMissEntries * DCacheWrapper: main pipe read should block refill pipe by set Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NLinJiawei <linjiav@outlook.com> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NJinYue <jinyue20s@ict.ac.cn> Co-authored-by:
Zhangfw <471348957@qq.com>
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- 11 10月, 2021 1 次提交
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由 Yinan Xu 提交于
* bump chisel to 3.5.0-RC1 We don't want to use SNAPSHOT version any more because we don't know what will happen when we wake up in the morning. * misc: remove TMA_* to avoid conflicts
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- 10 10月, 2021 1 次提交
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由 CODE-JTZ 提交于
* add soft prefetch Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to ld func unit. Then, we modified some interaction signals in ordinary Load steps.
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- 28 9月, 2021 1 次提交
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由 Yinan Xu 提交于
* rename Roq to Rob * remove trailing whitespaces * remove unused parameters
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- 27 9月, 2021 1 次提交
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由 Jiawei Lin 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * dcache: fix l1 probe index generate logic * Now right probe index will be used according to the len of alias bits * dcache: clean up amo pipeline * DCacheParameter rowBits will be removed in the future, now we set it to 128 to make dcache work * dcache: fix amo word index * bump huancun Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 16 9月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 13 9月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 11 9月, 2021 1 次提交
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由 zhanglinjuan 提交于
* MissQueue: send GrantAck immediately after first beat of GrantData * MissQueue: add perf cnts * MissQueue: fix assertion failure in perf cnt * MissQueue: add perf cnts for proportion of load merge / load reject * MissQueue: add perf cnt * MissQueue: fix merge-conflict error
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- 10 9月, 2021 1 次提交
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由 Jiawei Lin 提交于
* misc: add submodule huancun * huancun: integrate huancun to SoC as L3 * remove l2prefetcher * update huancun * Bump HuanCun * Use HuanCun instead old L2/L3 * bump huancun * bump huancun * Set L3NBanks to 4 * Update rocketchip * Bump huancun * Bump HuanCun * Optimize debug configs * Configs: fix L3 bug * Add TLLogger * TLLogger: fix release ack address * Support write prefix into database * Recoding more tilelink info * Add a database output format converter * missqueue: add difftest port for memory difftest during refill * misc: bump difftest * misc: bump difftest & huancun * missqueue: do not check refill data when get Grant * Add directory debug tool * config: increase client dir size for non-inclusive cache * Bump difftest and huancun * Update l2/l3 cache configs * Remove deprecated fpga/* * Remove cache test * Remove L2 preftecher * bump huancun * Params: turn on l2 prefetch by default * misc: remove duplicate chisel-tester2 * misc: remove sifive inclusive cache * bump difftest * bump huancun * config: use 4MB L3 cache * bump huancun * bump difftest * bump difftest Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn>
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- 01 9月, 2021 1 次提交
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由 William Wang 提交于
Update should_refill_data eariler to refill first half of refill data
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- 25 8月, 2021 2 次提交
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由 William Wang 提交于
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由 Yinan Xu 提交于
* Refactor print control transform * Adda tilelink bus pmu * Add performance counters for dispatch, issue, execute stages * Add more counters in bus pmu * Insert BusPMU between L3 and L2 * add some TMA perfcnt Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 24 8月, 2021 1 次提交
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由 William Wang 提交于
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 31 3月, 2021 1 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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- 25 3月, 2021 3 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 Allen 提交于
Not tested yet. Added: * L1 MSHR occupation * L1 MSHR latency * L1 Load Miss latency * L1 Store latency * L1 Store occupation * L1 Load req count
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由 wakafa 提交于
* perf: set acc arg of XSPerf as false by default * perf: add write-port competition counter for intBlock & floatBlock * perf: remove prefix of perf signal * perf: add perf-cnt for interface between frontend & backend * perf: modify perf-cnt for prefetchers * Ftq: bypass 'commit state' to fix dequeue bug * perf: uptimize perf-cnt in ctrlblock & ftq * perf: fix compilation problem in ftq * perf: remove duplicate perf-cnt * perf: calcu extra walk cycle exceeding frontend flush bubble * Revert "perf: calcu extra walk cycle exceeding frontend flush bubble" This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70. * perf: add perf-cnt for ifu * perf: add perf-cnt for rs * RS: optimize numExist signal * RS: fix some typo * perf: add QueuePerf util to monitor usage info of queues * perf: remove some duprecate perfcnt
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- 22 3月, 2021 1 次提交
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由 zhanglinjuan 提交于
* MissQueue: add perf cnt for inflight entries in maximum * MissQueue: max_inflight ignores cycles when missQueue is empty
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- 10 3月, 2021 1 次提交
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由 zhanglinjuan 提交于
* DCache: fix bug in failing to update access info of plru replacement * DCache: add performance counters
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- 03 3月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 02 3月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 01 3月, 2021 1 次提交
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由 allen 提交于
* DCache: remove ecc to improve timing. * MissQueue: refill_arb change RRArbiter to Arbiter to improve timing.
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- 24 2月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 23 2月, 2021 2 次提交
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由 zhanglinjuan 提交于
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由 wangkaifan 提交于
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- 20 2月, 2021 1 次提交
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由 zhanglinjuan 提交于
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- 09 2月, 2021 1 次提交
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由 wangkaifan 提交于
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- 26 1月, 2021 2 次提交
- 25 1月, 2021 2 次提交
- 24 1月, 2021 3 次提交