- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 18 4月, 2021 1 次提交
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由 Yinan Xu 提交于
Previously we RegNext sfence for ITLB and DTLB, but we ignored PTW. It will cause errors when both sfence.valid and req.fire() are set.
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- 16 4月, 2021 2 次提交
- 05 4月, 2021 2 次提交
- 04 4月, 2021 4 次提交
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由 Yinan Xu 提交于
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由 Steve Gou 提交于
* ras: partly handle stack overflow problems * ras: add overflow and underflow statistics
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由 Jay 提交于
useRefillReg is not be used when holdRead
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由 William Wang 提交于
FDivSqrt: update to srt4
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- 03 4月, 2021 2 次提交
- 02 4月, 2021 3 次提交
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由 Yinan Xu 提交于
Bump chisel to v3.4.3 and re-add `-X verilog` parameter for chisel runs. Our transform seems to have conflicts when `-X verilog` is not set.
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由 Yinan Xu 提交于
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由 allen 提交于
* Fixed perf counter does not print bug in BlockInclusiveCache. * BlockInclusiveCache: Dont Probe L1 On Hint Hit. * L2 use UncachedGet, L3 cache Get. * Bump L2 Co-authored-by: NLinJiawei <linjiav@outlook.com>
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- 01 4月, 2021 4 次提交
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由 Yinan Xu 提交于
* Add ResetRegGen module to generate reset signals for different modules To meet physical design requirements, reset signals for different modules need to be generated respectively. This commit adds a ResetRegGen module to automatically generate reset registers and connects different reset signals to different modules, including l3cache, l2cache, core. L1plusCache, MemBlock, IntegerBlock, FloatBlock, CtrlBlock, Frontend are reset one by one.
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由 Yinan Xu 提交于
* ICache: set holdRead to true for meta and data SRAMs SyncReadMem generates the verilog behavior model whose output rdata is always mem(RegNext(raddr)). Accidentally, ICache will not change meta and data SRAMs' raddr if the second pipeline stage is stalled (and ren is false). Thus, the SRAMs seem to have the holdRead property. Obviously, it will cause errors on real SRAMs. We set holdRead to true to fix the bug. * L1plusCache: set holdRead to true for SRAMs * Makefile: enable SRAM randomization for verilator simulation Previously we don't use the --infer-rw and --repl-seq-mem flags for simulation verilog. However, the SyncReadMem fails to generate random read data when ren is not set. In this commit, SyncReadMem is changed to blackboxes and generated by the vlsi_mem_gen script. RANDOMIZE_GARBAGE_ASSIGN flag is defined to enable randomization.
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由 Yinan Xu 提交于
SyncReadMem generates the verilog behavior model whose output rdata is always mem(RegNext(raddr)). Accidentally, ICache will not change meta and data SRAMs' raddr if the second pipeline stage is stalled (and ren is false). Thus, the SRAMs seem to have the holdRead property. Obviously, it will cause errors on real SRAMs. We set holdRead to true to fix the bug.
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由 Yinan Xu 提交于
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- 31 3月, 2021 5 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters * csr: bug fixing for perf-cnt wiring
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Jay 提交于
* AXIFlash: use blackbox to rebuild flash * device.cpp: add init_flash * Add flash.cpp for DPI-C funtion * Flash: use USE_BIN to enable FI from flash * AXIFlash: delete original flash
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- 30 3月, 2021 5 次提交
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 wakafa 提交于
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由 zhanglinjuan 提交于
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由 Yinan Xu 提交于
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- 29 3月, 2021 1 次提交
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由 wakafa 提交于
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- 28 3月, 2021 1 次提交
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由 allen 提交于
* Fixed perf counter does not print bug in BlockInclusiveCache. * Bump l2 Co-authored-by: NLinJiawei <linjiav@outlook.com>
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- 27 3月, 2021 1 次提交
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由 ljw 提交于
* L2/L3: set replacement policy to plru * Bump l2
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- 26 3月, 2021 7 次提交
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由 Yinan Xu 提交于
L1/L2 Add perf counters
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由 Allen 提交于
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由 Allen 提交于
L2 and L3 Only enablePerf when XSCore enables perf.
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由 Allen 提交于
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由 Wonicon 提交于
* l2,timing: bump l2/l3 cache This will necessarily add several cycles to L2/L3 cache responsing time. * l2,l3: bump timing tweaks Resolved timeout in debian boot. Remove repeat feature to avoid directory disturbing (repeat allows to use previous tag and victim info which is dangerous). TODO: - [ ] Another directory atomicity weakness that heavy l1 release can overwrite l3tol2 probe directory update, for example: l1.rel.TtoB write dirty -> l1.rel.BtoN readout dirty then writeback l2.probeAck.BtoB write non-dirty (not saved) l3 think l2 is branch, but l2 is still trunk. But forbid nestB and nestC can cause deadlock... - [ ] Delay bankedStore one more cycle for L3 large sram timing. * l2,l3: change mshr amount to 15
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由 Lemover 提交于
* RS: fix bug that fp src's flushed enqueue conflicts with next enqueue * RS: fix bug that ctrl's flushed enqueue conflicts with next enqueue
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- 25 3月, 2021 1 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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