Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* remove base table and use ftb results as base pred
* add corrsponding redirect logic in bpu

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
  in order to remove casting operation in composer

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* block reads when ittage writes
* reset ras on reset so that it would not provide random addresses

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

* let tage SRAM writes cover reads, ignoring read data
* let wrbypass to be 16 entries

* use a single bit for each entry and adopt the reset mechanism introduced in TAGE-SC-L
* use regfile instead of SRAMs to store u bits

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top