* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for peripheral port

* Fix submodule version

* sbuffer: do flush correctly while draining sbuffer

* ci: enable ci for timing-memblock branch

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we simplily block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* WritebackQueue: optimize enqueue logic fir timing

* WritebackQueue: always reject a req when wbq is full

* Revert "ci: enable ci for timing-memblock branch"

This reverts commit 32453dc4.

* WritebackQueue: fix bug in secondary_valid
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

* Filter: hit dont care asid for when asid change, flush all

* TLB: timing opt in hitppn and hitperm Mux

* l2tlb.filter: timing opt in enqueue filter logic

add one more cycle when enq to break up tlb's hit check and filter's
dup check.

so there are 3 stage: regnext -> enqueue -> issue
when at regnext stage:
  1. regnext after filter with ptw_resp
  2. do 'same vpn' check with
    1) old entries &
    2) new reqs &
    3) old reqs.
    but don't care new reqs'valid
when at enqueue stage:
  use last stage(regnext)'s result with valid signal at this stage
  to check if duplicate or not. update ports or enq ptr, et al.
  alse **optimize enqPtrVec generating logic**
  also **optimize do_iss generating logic**

* TLB: add fast_miss that dontcare sram's hit result

* L2TLB.filter: move lastReqMatch to first stage

* bku: add one more cycle of latency

* bku: support pipeline stalls

* Clean up project dependencies

* Update README

* Fix typo

* bump huancun

* bump huancun

* bump huancun

* dcache: merge replace pipe with main pipe for timing reason

* MainPipe: fix bug in s3_fire

* MainPipe: fix bug in delay_release sent to wbq

* MainPipe: fix bug in blocking policy

* MainPipe: send io.replace_resp in stage 3

* MainPipe: fix bug in miss_id sent to wbq

* MainPipe: fix bug
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

bpu timing optimization

* sbuffer: do flush correctly while draining sbuffer

* mem: disable EnableFastForward for timing reasons

* sbuffer: optimize forward mask gen timing

* dcache: block main pipe req if refill req is valid

Refill req comes from refill arbiter. There is not time left for index
conflict check. Now we block all main pipe req when refill
req comes from miss queue.

* dcache: delay some resp signals for better timing

* dcache: optimize wbq enq entry select timing

* dcache: decouple missq req.valid to valid & cancel

* valid is fast, it is used to select which miss req will be sent to
miss queue
* cancel can be slow to generate, it will cancel miss queue req in the
last moment

* sbuffer: optimize noSameBlockInflight check timing

* bump difftest

* ICache: metaArray & dataArray use bank interleave

* ICache: add bank interleave

* ICache: add parity check for meta and data arrays

* IFU: fix bug in secondary miss

* secondary miss doesn't send miss request to miss queue

* ICache: write back cancled miss request

* ICacheMissEntry: add second miss merge

* deal with situations that this entry has been flushed, and the next miss req just
requests the same cachline.

* ICache: add acquireBlock and GrantAck support

* refact: move icache modules to frontend modules

* ICache: add release surport and meta coh

* ICache: change Get to AcquireBlock for A channel

* rebuild: change ICachePara package for other file

* ICache: add tilelogger for L1I

* ICahce: add ProbeQueue and Probe Process Unit

* ICache: add support for ProbeData

* ICahceParameter: change tag code to ECC

* ICahce: fix bugs in connect and ProbeUnit

* metaArray/dataArray responses are not connected

* ProbeUnit use reg so data and req are not synchronized

* RealeaseUnit: write back mata when voluntary

* Add ICache CacheInstruction

* move ICache to xiangshan.frontend.icache._

* ICache: add CacheOpDecoder

* change ICacheMissQueue to ICacheMissUnit

* ProbeUnit: fix meta data not latch bug

* IFU: delete releaseSlot and add missSlot

* IFU: fix bugs in missSlot state machine

* IFU: fix some bugs in miss Slot

* IFU: move out fetch to ICache Array logic

* ReleaseUnit: delete release write logic

* MissUnit: send Release to ReleaseUnit after GAck

* ICacheMainPipe: add mainpipe and stop logic

* when f3_ready is low, stop the pipeline

* IFU: move tlb and array access to mainpipe

* Modify Frontend and ICache top for mainpipe

* ReleaseUnit: add probe merge status register

* ICache: add victim info and release in mainpipe

* ICahche: add set-conflict logic

* Release: do not invalid meta after sending release

* bump Huancun: fix probe problem

* bump huancun for MinimalConfig combinational loop

* ICache: add LICENSE for new files

* Chore: remove debug code and add perf counter

* Bump huancun for bug fix

* Bump HuanCun for alias bug

* ICache: add dirty state for CliendMeta

* use one hot muxes for ftb read resp
* generate branch history shift one hot vec for history update src sel
  and update for all possible shift values

This commit optimizes instruction fusion detection logic for fused
addw{byte, bit, zexth, sexth}, mulw7, and logic{lsb, zexth}
instructions.

Previously we use fuType and fuOpType from the normal decoder, and this
incurs a bad timing. Now we change the detection logic to use only the
raw instructions. Though the fused instruction still uses the
fuOpType from the normal decoder, there should be only serveral MUXes
left.

ftq: optimize ifu request timing

update hpmevent defalt value and write mask; modify fetch trigger res…

This commit changes how isFreed is calculated. Instead of using
refCounter in the next, we compute it at this cycle and RegNext it.

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

ftq: code clean ups

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a
"speculatively assigned" sqIdx, as it is hard to track store insts in
dispatch queue. Yet we can still use "speculatively assigned" robIdx
for memory dependency predictor.

For now, memory dependency predictor uses "speculatively assigned"
robIdx to track inflight store.

However, sqIdx is still used to track those store which's addr is valid
but data it not valid. When load insts try to get forward data from
those store, load insts will get that store's sqIdx and wait in RS.
They will not waken until store data with that sqIdx is issued.

* mdp: add track robIdx recover logic

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2