This commit adds separated redirect registers in ExuBlock and MemBlock.
They have one cycle latency compared to redirect in CtrlBlock. This will
help reduce the fanout of redirect registers.

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset

This commit adds load balance strategy in issue selection logic for
reservation stations.

Previously we have a load balance option in ExuBlock, but it cannot work
if the function units have feedbacks to RS. In this commit it is
removed.

This commit adds a victim index option for oldestFirst. For LOAD, the
first issue port has better performance and thus we set the victim index
to 0. For other function units, we use the last issue port.

This commit adds assertion in MaskData to check the width of mask
and data. When the width of mask is smaller than the width of data,
(~mask & data) and (mask & data) will always clear the upper bits
of the data. This usually causes unexpected behavior.

This commit adds explicit width declarations where MaskData is used.

XiangShan is jointly released by ICT and PCL.

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataModuleTemplate
* should only bypass data between the same addr when allocate.valid

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataModuleTemplate
* should only bypass data between the same addr when allocate.valid

In this commit, we add License for XiangShan project. 

* WaitTable: add waittable framework

* WaitTable: get replay info from RedirectGenerator

* StoreQueue: maintain issuePtr for load rs

* RS: add loadWait to rs (only for load Unit's rs)

* WaitTable: fix update logic

* StoreQueue: fix issuePtr update logic

* chore: set loadWaitBit in ibuffer

* StoreQueue: fix issuePtrExt update logic

Former logic does not work well with mmio logic

We may also make sure that issuePtrExt is not before cmtPtrExt

* WaitTable: write with priority

* StoreQueue: fix issuePtrExt update logic for mmio

* chore: fix typos

* CSR: add slvpredctrl

* slvpredctrl will control load violation predict micro architecture

* WaitTable: use xor folded pc to index waittable
Co-authored-by: NZhangZifei <1773908404@qq.com>

Now, it can compile.

Now mshrs can end transaction and go to replay.

Just compiles.