- 26 7月, 2022 1 次提交
-
-
由 William Wang 提交于
Now we use tag_write_intend to generate ready signal for load issue It should remove the critical path from dcacheReq.ready to rs
-
- 25 7月, 2022 3 次提交
-
-
由 Steve Gou 提交于
ras: delay write for 1 cycle and bypass write to read
-
由 Lemover 提交于
Add bypassed logic of refill logic, to prevent duplicate mem access due to wrongly miss. Not actually forward the data, just check if vpn hit and re-access the page cache. Add some asserts to prevent duplicate mem access. These assert maybe wrongly triggered in some corner case. * l2tlb: add assert that do not allow duplicate mem access * l2tlb: change dup mem access assert to dup mem resp assert * l2tlb: when refill after access page cache, re-access page cache * l2tlb: fix assert signal that wrong assigned * l2tlb: store empty super page to sp entries * l2tlb: fix bug that lost req due to bypassed req not enq mq * l2tlb: fix bug that lost req due to bypassed req not enq mq * l2tlb: fix bug of cache resp ready logic * l2tlb.cache: fix bug of vpn bypass match * l2tlb.cache: fix bug of vs anticipate into hit check
-
由 Lemover 提交于
* l1tlb: for non-block tlb port, resp should always be ready * l1tlb: add tlb refill duplicate assert
-
- 24 7月, 2022 5 次提交
-
-
由 Yinan Xu 提交于
This commit changes the allocation policy in Store Set memory dependence predictor. Previously we allocate an entry for the load and store instructions every time when a memory violation is triggered. However, it's not robust enough and causes many load instructions to be blocked for issuing. The current allocation policy only allocates the same entry for the load and store instructions after both of them have triggered memory violations before. That is to say, only when a load/store instruction pair triggers memory violation twice, we do allocate the same entry to them. This change may cause more memory violation redirections than before, but it also reduces the number of blocked load instructions.
-
由 Yinan Xu 提交于
This commit fixes the wrong update values of commitInstr in ROB. Previously we add a RegNext to trueCommitCnt in #1644. However, we don't add RegNext to the ifCommit condition. This makes the commitInstr larger than the normal value and IPC looks better. This commit fixes this bug and the IPC numbers should be correct now.
-
由 wakafa 提交于
-
由 zhanglinjuan 提交于
-
由 William Wang 提交于
Note that it is intend to prevent X prop in simulation, may cause timing problem. These check can be removed safely for better timing
-
- 21 7月, 2022 2 次提交
- 19 7月, 2022 2 次提交
- 18 7月, 2022 3 次提交
-
-
由 Yinan Xu 提交于
* ftq, ctrl: remove pc/target backend read ports, and remove redirectGen in ftq * ctrl: add data modules for pc and jalr_target This commit adds two data modules for pc and jalr_target respectively. They are the same as data modules in frontend. Should benefit timing. * jump: reduce pc and jalr_target read latency * ftq: add predecode redirect update target interface, valid only on ifuRedirect * ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
-
由 Lemover 提交于
DTLB volume configuration: old: normal page 128 direct-asso + super page 8 full-asso new: normal page 64 direct-asso + super page 16 full-asso Better timing and better driver now. For Spec06,some specs increase slightly, while some others decrease slightly.
-
由 Lemover 提交于
each tlb's port can be configured to be block or non-blocked. For blocked port, there will be a req miss slot stored in tlb, but belong to core pipeline, which means only core pipeline flush will invalid them. For another, itlb also use PTW Filter but with only 4 entries. Last, keep svinval extension as usual, still work. * tlb: add blocked-tlb support, miss frontend changes * tlb: remove tlb's sameCycle support, result will return at next cycle * tlb: remove param ShouldBlock, move block method into TLB module * tlb: fix handle_block's miss_req logic * mmu.filter: change filter's req.ready to canEnqueue when filter can't let all the req enqueue, set the req.ready to false. canEnqueue after filtering has long latency, so we use **_fake without filtering, but the filter will still receive the reqs if it can(after filtering). * mmu.tlb: change name from BTlbPtwIO to VectorTlbPtwIO * mmu: replace itlb's repeater to filter&repeaternb * mmu.tlb: add TlbStorageWrapper to make TLB cleaner more: BlockTlbRequestorIO is same with TlbRequestorIO, rm it * mmu.tlb: rm unused param in function r_req_apply, fix syntax bug * [WIP]icache: itlb usage from non-blocked to blocked * mmu.tlb: change parameter NBWidth to Seq of boolean * icache.mainpipe: fix itlb's resp.ready, not always true * mmu.tlb: add kill sigal to blocked req that needs sync but fail in frontend, icache,itlb,next pipe may not able to sync. blocked tlb will store miss req ang blocks req, which makes itlb couldn't work. So add kill logic to let itlb not to store reqs. One more thing: fix icache's blocked tlb handling logic * icache.mainpipe: fix tlb's ready_recv logic icache mainpipe has two ports, but these two ports may not valid all the same time. So add new signals tlb_need_recv to record whether stage s1 should wait for the tlb. * tlb: when flush, just set resp.valid and pf, pf for don't use it * tlb: flush should concern satp.changed(for blocked io now) * mmu.tlb: add new flush that doesn't flush reqs Sfence.vma will flush inflight reqs and flushPipe But some other sfence(svinval...) will not. So add new flush to distinguish these two kinds of sfence signal morw: forget to assign resp result when ptw back, fix it * mmu.tlb: beautify miss_req_v and miss_v relative logic * mmu.tlb: fix bug, when ptw back and bypass, concern level to genPPN bug: when ptw back and bypass, forgot to concern level(1GB/2MB/4KB) when genPPN. by the way: some funtions need ": Unit = ", add it. * mmu.filter: fix bug of canEnqueue, mixed with tlb_req and tlb.req * icache.mainpipe: fix bug of tlbExcp's usage, & with tlb_need_back Icache's mainpipe has two ports, but may only port 0 is valid. When a port is invalid, the tlbexcp should be false.(Actually, should be ignored). So & tlb_need_back to fix this bug. * sfence: instr in svinval ext will also flush pipe A difficult problem to handle: Sfence and Svinval will flush MMU, but only Sfence(some svinval) will flush pipe. For itlb that some requestors are blocked and icache doesn't recv flush for simplicity, itlb's blocked ptw req should not be flushed. It's a huge problem for MMU to handle for good or bad solutions. But svinval is seldom used, so disable it's effiency. * mmu: add parameter to control mmu's sfence delay latency Difficult problem: itlb's blocked req should not be abandoned, but sfence will flush all infight reqs. when itlb and itlb repeater's delay is not same(itlb is flushed, two cycles later, itlb repeater is flushed, then itlb's ptw req after flushing will be also flushed sliently. So add one parameter to control the flush delay to be the same. * mmu.tlb: fix bug of csr.priv's delay & sfence valid when req fire 1. csr.priv's delay csr.priv should not be delayed, csr.satp should be delayed. for excep/intr will change csr.priv, which will be changed at one instruction's (commit?). but csrrw satp will not, so satp has more cycles to delay. 2. sfence when sfence valid but blocked req fire, resp should still fire. 3. satp in TlbCsrBundle let high bits of satp.ppn to be 0.U * tlb&icache.mainpipe: rm commented codes * mmu: move method genPPN to entry bundle * l1tlb: divide l1tlb flush into flush_mmu and flush_pipe Problem: For l1tlb, there are blocked and non-blocked req ports. For blocked ports, there are req slots to store missed reqs. Some mmu flush like Sfence should not flush miss slots for outside may still need get tlb resp, no matter wrong and correct resp. For example. sfence will flush mmu and flush pipe, but won't flush reqs inside icache, which waiting for tlb resp. For example, svinval instr will flush mmu, but not flush pipe. so tlb should return correct resp, althrough the ptw req is flushed when tlb miss. Solution: divide l1tlb flush into flush_mmu and flush_pipe. The req slot is considered to be a part of core pipeline and should only be flushed by flush_pipe. flush_mmu will flush mmu entries and inflight ptw reqs. When miss but sfence flushed its ptw req, re-send. * l1tlb: code clean, correct comments and rm unused codes * l2tlb: divide filterSize into ifiterSize and dfilterSize * l2tlb: prefetch req won't enter miss queue. Rename MSHR to missqueue * l1tlb: when disable vm, ptw back should not bypass tlb and should let miss req go ahead
-
- 16 7月, 2022 3 次提交
-
-
由 William Wang 提交于
It should remove dtlb to rs critical path
-
由 William Wang 提交于
replace_pipe_req is causing timing problem as vaddr in it is used to generate mainpipe block signal. Unfortunately, vaddr from replace_pipe_req is selected form all miss queue entries (16 by default), which caused timing problem refill_pipe_req will not be scheduled until dcache main pipe s3 reports that replace_pipe_req has been finished. Thus it is legal to add a pipe reg for replace_pipe_req Now ALL mainpipe req candidates come from pipe reg. At the entry of main pipe, 1 req is selected from 4 main pipe reqs, and its vaddr is used to calcuate set block condition
-
由 Lingrui98 提交于
-
- 15 7月, 2022 2 次提交
-
-
由 Yinan Xu 提交于
* scheduler: fix performance counter timing * rs: optimize allocation ready gen timing
-
由 William Wang 提交于
Optimize nanhu lsu timing
-
- 14 7月, 2022 5 次提交
-
-
由 Yinan Xu 提交于
* rob: separate walk and commit valid bits * rob: optimize instrCnt timing * rob: fix blockCommit condition when flushPipe When flushPipe is enabled, it will block commits in ROB. However, in the deqPtrModule, the commit is not blocked. This commit fixes the issue.
-
由 Lemover 提交于
Old Edition: 2 ld tlb but with same entries. 2 st tlb but wih the same entries. The 'duplicate' is used for timing optimization that each tlb can be placed close to mem access pipeline unit. Problem: The duplicate tlb takes more Power/Area. New Edition: Only 1 ld tlb and 1 st tlb now. If the area is not ok, may merge ld and st together. Fix: fix some syntax bug when changing parameters
-
由 Yinan Xu 提交于
Balance between the first numDeq ports. Possible IPC increase?
-
由 Lemover 提交于
* l1tlb: l1tlb entry uses one-hot size * l1tlb: fix victim write when level usage changes
-
由 Yinan Xu 提交于
* ibuf: optimize register namings * ibuffer: re-write data read logic
-
- 13 7月, 2022 3 次提交
-
-
由 Yinan Xu 提交于
* dpq: add slow path for non-critical registers This commit separates the data module in Dispatch to slow and fast path. Slow path stores the data with a bad timing at Dispatch but a good timing at Dispatch2. Thus should benefit the timing at Dispatch, such as the LFST. For now, we merge the slow and fast data module. Chisel DCE does not eliminate the dead registers. We manully merge the two data modules for now. * dpq: optimize timing for enqPtr/deqPtr matching This commit optimizes the matching timing between enqPtr and deqPtr, which is used further for bypassing enqData to deqData. Now enqOffset and deqPtr/enqPtr matching work in parallel.
-
由 Yinan Xu 提交于
This commit moves the decoder of software prefetch instructions to the rename stage. Previously the decoding of software prefetch instructions affects the imm gen and causes a long critical path.
-
由 Yinan Xu 提交于
* utils: optimize the timing of OnesMoreThan * utils: fix XORFold width
-
- 12 7月, 2022 8 次提交
-
-
由 William Wang 提交于
-
由 William Wang 提交于
This commit adds an extra cycle for load pipeline. It should fix timing problem caused by load pipeline. Huge perf loss is expected. Now load data result is sent to rs in load_s3, load may hit hint (fastUop.valid) is sent to rs in load_s2. We add a 3 cycle load to load fast forward data path. There should be enough time to forward data inside memory block. We will refactor code and add a load_s3 module in the future. BREAKING CHANGE: load pipeline reorginized
-
由 Yinan Xu 提交于
* rat: map all arch registers to zero when init * freelist: fix stepBack width * freelist: fix timing of free offset
-
由 zhanglinjuan 提交于
-
由 Yinan Xu 提交于
-
由 Yinan Xu 提交于
* ctrl: copy dispatch2 to avoid cross-module loops This commit makes copies of dispatch2 in CtrlBlock to avoid long cross-module timing loop paths. Should be good for timing. * dpq: re-write queue read logic This commit adds a Reg-Vec to store the queue read data. Since most queues read at most the current numRead and the next numRead entries, the read timing can be optimized by reading the data one cycle earlier.
-
由 Yinan Xu 提交于
This commit optimizes the timing of reservation stations. * dispatched uops are latched and bypassed to s1_out * wakeup from slowPorts are latched and bypassed to s1_data * rs: optimize allocation selection Change select policy for allocation. Should avoid issuing the just dispatched instructions in some cases. * rs: disable load balance for load units
-
由 Yinan Xu 提交于
The VGA device may cause assertions in AXI4SlaveModule because it may send arbitrary requests to fb (AXI4RAM).
-
- 11 7月, 2022 2 次提交
-
-
由 Yinan Xu 提交于
This commit fixes the bug that instructions with exceptions may trigger instruction fusion if the previous instruction at the same position is fused. When the input instruction pair is invalid, the fusion decoder should always set out.valid to false.B at the next cycle. The bug is caused by the RegEnable for instrPairValid, which should be updated at every clock cycle. Should fix the error introduced by 0febc381 and the regression failure at https://github.com/OpenXiangShan/XiangShan/actions/runs/2645135867.
-
由 William Wang 提交于
dcache: optimize timing for probe req entering main pipe MissQueue: use FastArbiter for replace req
-
- 10 7月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
This commit adds separated redirect registers in ExuBlock and MemBlock. They have one cycle latency compared to redirect in CtrlBlock. This will help reduce the fanout of redirect registers.
-