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体验新版 GitCode,发现更多精彩内容 >>
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f698fe9c
编写于
12月 17, 2020
作者:
Y
Yinan Xu
浏览文件
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电子邮件补丁
差异文件
dtlb: don't select refill entry when ptw.resp.fire
上级
25c195c7
变更
1
显示空白变更内容
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并排
Showing
1 changed file
with
28 addition
and
17 deletion
+28
-17
src/main/scala/xiangshan/cache/dtlb.scala
src/main/scala/xiangshan/cache/dtlb.scala
+28
-17
未找到文件。
src/main/scala/xiangshan/cache/dtlb.scala
浏览文件 @
f698fe9c
...
@@ -273,8 +273,32 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
...
@@ -273,8 +273,32 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
entry
=
Reg
(
Vec
(
TlbEntrySize
,
new
TlbEntry
))
val
entry
=
Reg
(
Vec
(
TlbEntrySize
,
new
TlbEntry
))
val
g
=
VecInit
(
entry
.
map
(
_
.
perm
.
g
)).
asUInt
// TODO: need check if reverse is needed
val
g
=
VecInit
(
entry
.
map
(
_
.
perm
.
g
)).
asUInt
// TODO: need check if reverse is needed
/**
* PTW refill
*/
val
refill
=
ptw
.
resp
.
fire
()
val
randIdx
=
LFSR64
()(
log2Up
(
TlbEntrySize
)-
1
,
0
)
val
priorIdx
=
PriorityEncoder
(~(
v
|
pf
))
val
tlbfull
=
ParallelAND
((
v
|
pf
).
asBools
)
val
refillIdx
=
Mux
(
tlbfull
,
randIdx
,
priorIdx
)
val
refillIdxOH
=
UIntToOH
(
refillIdx
)
when
(
refill
)
{
v
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
v
&
~
refillIdxOH
,
v
|
refillIdxOH
)
entry
(
refillIdx
)
:=
ptw
.
resp
.
bits
.
entry
XSDebug
(
p
"Refill: idx:${refillIdx} entry:${ptw.resp.bits.entry}\n"
)
}
/**
* L1 TLB read
*/
val
tlb_read_mask
=
Mux
(
refill
,
refillIdxOH
,
0.
U
(
TlbEntrySize
.
W
))
def
TLBRead
(
i
:
Int
)
=
{
def
TLBRead
(
i
:
Int
)
=
{
val
entryHitVec
=
VecInit
(
entry
.
map
(
_
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)))
val
entryHitVec
=
(
if
(
isDtlb
)
VecInit
((
tlb_read_mask
.
asBools
zip
entry
).
map
{
case
(
r
,
e
)
=>
!
r
&&
e
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)})
else
VecInit
(
entry
.
map
(
_
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)))
)
val
reqAddrReg
=
if
(
isDtlb
)
RegNext
(
reqAddr
(
i
))
else
reqAddr
(
i
)
val
reqAddrReg
=
if
(
isDtlb
)
RegNext
(
reqAddr
(
i
))
else
reqAddr
(
i
)
val
cmdReg
=
if
(
isDtlb
)
RegNext
(
cmd
(
i
))
else
cmd
(
i
)
val
cmdReg
=
if
(
isDtlb
)
RegNext
(
cmd
(
i
))
else
cmd
(
i
)
...
@@ -364,25 +388,12 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
...
@@ -364,25 +388,12 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
pfHitReset
=
ParallelOR
(
widthMap
{
i
=>
Mux
(
resp
(
i
).
fire
(),
VecInit
(
pfHitVecVec
(
i
)).
asUInt
,
0.
U
)
})
val
pfHitReset
=
ParallelOR
(
widthMap
{
i
=>
Mux
(
resp
(
i
).
fire
(),
VecInit
(
pfHitVecVec
(
i
)).
asUInt
,
0.
U
)
})
val
pfHitRefill
=
ParallelOR
(
pfHitReset
.
asBools
)
val
pfHitRefill
=
ParallelOR
(
pfHitReset
.
asBools
)
// refill
val
refill
=
ptw
.
resp
.
fire
()
val
randIdx
=
LFSR64
()(
log2Up
(
TlbEntrySize
)-
1
,
0
)
val
priorIdx
=
PriorityEncoder
(~(
v
|
pf
))
val
tlbfull
=
ParallelAND
((
v
|
pf
).
asBools
)
val
refillIdx
=
Mux
(
tlbfull
,
randIdx
,
priorIdx
)
val
re2OH
=
UIntToOH
(
refillIdx
)
when
(
refill
)
{
v
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
v
&
~
re2OH
,
v
|
re2OH
)
entry
(
refillIdx
)
:=
ptw
.
resp
.
bits
.
entry
XSDebug
(
p
"Refill: idx:${refillIdx} entry:${ptw.resp.bits.entry}\n"
)
}
// pf update
// pf update
when
(
refill
)
{
when
(
refill
)
{
when
(
pfHitRefill
)
{
when
(
pfHitRefill
)
{
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
2OH
,
pf
&
~
re2
OH
)
&
~
pfHitReset
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
fillIdxOH
,
pf
&
~
refillIdx
OH
)
&
~
pfHitReset
}
.
otherwise
{
}
.
otherwise
{
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
2OH
,
pf
&
~
re2
OH
)
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
fillIdxOH
,
pf
&
~
refillIdx
OH
)
}
}
}
.
otherwise
{
}
.
otherwise
{
when
(
pfHitRefill
)
{
when
(
pfHitRefill
)
{
...
@@ -390,7 +401,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
...
@@ -390,7 +401,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
}
}
}
}
when
(
PopCount
(
pf
)
>
10.
U
)
{
// when too much pf, just clear
when
(
PopCount
(
pf
)
>
10.
U
)
{
// when too much pf, just clear
pf
:=
Mux
(
refill
&&
ptw
.
resp
.
bits
.
pf
,
re
2
OH
,
0.
U
)
pf
:=
Mux
(
refill
&&
ptw
.
resp
.
bits
.
pf
,
re
fillIdx
OH
,
0.
U
)
}
}
// sfence (flush)
// sfence (flush)
...
...
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