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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
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f45bae9c
编写于
8月 18, 2021
作者:
L
Lingrui98
浏览文件
操作
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电子邮件补丁
差异文件
ftq: fix ifu req logic
上级
f8fc11f1
变更
2
显示空白变更内容
内联
并排
Showing
2 changed file
with
37 addition
and
16 deletion
+37
-16
src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
...n/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
+6
-0
src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
+31
-16
未找到文件。
src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala
浏览文件 @
f45bae9c
...
@@ -29,6 +29,12 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
...
@@ -29,6 +29,12 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
val
target
=
UInt
(
VAddrBits
.
W
)
val
target
=
UInt
(
VAddrBits
.
W
)
val
oversize
=
Bool
()
val
oversize
=
Bool
()
def
fallThroughError
()
=
{
def
carryPos
=
instOffsetBits
+
log2Ceil
(
PredictWidth
)+
1
def
getLower
(
pc
:
UInt
)
=
pc
(
instOffsetBits
+
log2Ceil
(
PredictWidth
),
instOffsetBits
)
val
carry
=
startAddr
(
carryPos
)
=/=
fallThruAddr
(
carryPos
)
carry
&&
getLower
(
startAddr
)
>
getLower
(
fallThruAddr
)
}
override
def
toPrintable
:
Printable
=
{
override
def
toPrintable
:
Printable
=
{
p
"[start] ${Hexadecimal(startAddr)} [pft] ${Hexadecimal(fallThruAddr)}"
+
p
"[start] ${Hexadecimal(startAddr)} [pft] ${Hexadecimal(fallThruAddr)}"
+
p
"[tgt] ${Hexadecimal(target)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}"
+
p
"[tgt] ${Hexadecimal(target)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}"
+
...
...
src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala
浏览文件 @
f45bae9c
...
@@ -382,8 +382,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -382,8 +382,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
io
.
fromBpu
.
resp
.
ready
:=
validEntries
<
FtqSize
.
U
io
.
fromBpu
.
resp
.
ready
:=
validEntries
<
FtqSize
.
U
val
enq_fire
=
io
.
fromBpu
.
resp
.
fire
()
&&
allowBpuIn
val
enq_fire
=
io
.
fromBpu
.
resp
.
fire
()
&&
allowBpuIn
// read ports: jumpPc + redirects + loadPred + roqFlush + ifuReq + commitUpdate
// read ports: jumpPc + redirects + loadPred + roqFlush + ifuReq
1 + ifuReq2
+ commitUpdate
val
ftq_pc_mem
=
Module
(
new
SyncDataModuleTemplate
(
new
Ftq_RF_Components
,
FtqSize
,
1
+
numRedirect
+
2
+
1
+
1
,
1
))
val
ftq_pc_mem
=
Module
(
new
SyncDataModuleTemplate
(
new
Ftq_RF_Components
,
FtqSize
,
1
+
numRedirect
+
2
+
1
+
1
+
1
,
1
))
ftq_pc_mem
.
io
.
wen
(
0
)
:=
enq_fire
ftq_pc_mem
.
io
.
wen
(
0
)
:=
enq_fire
ftq_pc_mem
.
io
.
waddr
(
0
)
:=
bpuPtr
.
value
ftq_pc_mem
.
io
.
waddr
(
0
)
:=
bpuPtr
.
value
ftq_pc_mem
.
io
.
wdata
(
0
).
startAddr
:=
io
.
fromBpu
.
resp
.
bits
.
pc
ftq_pc_mem
.
io
.
wdata
(
0
).
startAddr
:=
io
.
fromBpu
.
resp
.
bits
.
pc
...
@@ -533,26 +533,41 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -533,26 +533,41 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
val
bpu_enq_bypass_buf
=
RegEnable
(
ftq_pc_mem
.
io
.
wdata
(
0
),
enable
=
enq_fire
)
val
bpu_enq_bypass_buf
=
RegEnable
(
ftq_pc_mem
.
io
.
wdata
(
0
),
enable
=
enq_fire
)
val
bpu_enq_bypass_ptr
=
RegNext
(
bpuPtr
)
val
bpu_enq_bypass_ptr
=
RegNext
(
bpuPtr
)
val
last_cycle_bpu_enq
=
RegNext
(
enq_fire
)
val
last_cycle_bpu_enq
=
RegNext
(
enq_fire
)
val
last_cycle_to_ifu_fire
=
RegNext
(
io
.
toIfu
.
req
.
fire
)
// read pc and target
// read pc and target
ftq_pc_mem
.
io
.
raddr
.
init
.
last
:=
ifuPtr
.
value
ftq_pc_mem
.
io
.
raddr
.
init
.
init
.
last
:=
ifuPtr
.
value
ftq_pc_mem
.
io
.
raddr
.
init
.
last
:=
(
ifuPtr
+
1.
U
).
value
io
.
toIfu
.
req
.
valid
:=
allowToIfu
&&
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
&&
ifuPtr
=/=
bpuPtr
val
toIfuReq
=
Wire
(
chiselTypeOf
(
io
.
toIfu
.
req
))
io
.
toIfu
.
req
.
bits
.
ftqIdx
:=
ifuPtr
io
.
toIfu
.
req
.
bits
.
target
:=
update_target
(
ifuPtr
.
value
)
toIfuReq
.
valid
:=
allowToIfu
&&
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
&&
ifuPtr
=/=
bpuPtr
io
.
toIfu
.
req
.
bits
.
ftqOffset
:=
cfiIndex_vec
(
ifuPtr
.
value
)
toIfuReq
.
bits
.
ftqIdx
:=
ifuPtr
io
.
toIfu
.
req
.
bits
.
startAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
startAddr
toIfuReq
.
bits
.
target
:=
update_target
(
ifuPtr
.
value
)
io
.
toIfu
.
req
.
bits
.
fallThruAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
getFallThrough
()
toIfuReq
.
bits
.
ftqOffset
:=
cfiIndex_vec
(
ifuPtr
.
value
)
io
.
toIfu
.
req
.
bits
.
oversize
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
oversize
when
(
last_cycle_bpu_enq
&&
bpu_enq_bypass_ptr
===
ifuPtr
)
{
when
(
last_cycle_bpu_enq
&&
bpu_enq_bypass_ptr
===
ifuPtr
)
{
io
.
toIfu
.
req
.
bits
.
startAddr
:=
bpu_enq_bypass_buf
.
startAddr
toIfuReq
.
bits
.
startAddr
:=
bpu_enq_bypass_buf
.
startAddr
io
.
toIfu
.
req
.
bits
.
fallThruAddr
:=
bpu_enq_bypass_buf
.
getFallThrough
()
toIfuReq
.
bits
.
fallThruAddr
:=
bpu_enq_bypass_buf
.
getFallThrough
()
io
.
toIfu
.
req
.
bits
.
oversize
:=
bpu_enq_bypass_buf
.
oversize
toIfuReq
.
bits
.
oversize
:=
bpu_enq_bypass_buf
.
oversize
when
(
bpu_enq_bypass_buf
.
fallThroughError
()
&&
entry_hit_status
(
ifuPtr
.
value
)
===
h_hit
)
{
}.
elsewhen
(
last_cycle_to_ifu_fire
)
{
entry_hit_status
(
ifuPtr
.
value
)
===
h_false_hit
toIfuReq
.
bits
.
startAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
startAddr
toIfuReq
.
bits
.
fallThruAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
getFallThrough
()
toIfuReq
.
bits
.
oversize
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
last
.
oversize
}.
otherwise
{
toIfuReq
.
bits
.
startAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
init
.
last
.
startAddr
toIfuReq
.
bits
.
fallThruAddr
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
init
.
last
.
getFallThrough
()
toIfuReq
.
bits
.
oversize
:=
ftq_pc_mem
.
io
.
rdata
.
init
.
init
.
last
.
oversize
}
}
io
.
toIfu
.
req
<>
toIfuReq
// when fall through is smaller in value than start address, there must be a false hit
when
(
toIfuReq
.
bits
.
fallThroughError
()
&&
entry_hit_status
(
ifuPtr
.
value
)
===
h_hit
)
{
entry_hit_status
(
ifuPtr
.
value
)
===
h_false_hit
io
.
toIfu
.
req
.
bits
.
fallThruAddr
:=
toIfuReq
.
bits
.
startAddr
+
(
FetchWidth
*
4
).
U
}
}
when
(
io
.
toIfu
.
req
.
fire
)
{
when
(
io
.
toIfu
.
req
.
fire
)
{
entry_fetch_status
(
ifuPtr
.
value
)
:=
f_sent
entry_fetch_status
(
ifuPtr
.
value
)
:=
f_sent
}
}
...
...
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