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c15d13ad
编写于
10月 23, 2022
作者:
Z
ZhangZifei
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
issue: delete fma midState relative codes
上级
92ab0b2e
变更
10
显示空白变更内容
内联
并排
Showing
10 changed file
with
12 addition
and
204 deletion
+12
-204
src/main/scala/xiangshan/backend/ExuBlock.scala
src/main/scala/xiangshan/backend/ExuBlock.scala
+0
-3
src/main/scala/xiangshan/backend/FUBlock.scala
src/main/scala/xiangshan/backend/FUBlock.scala
+0
-6
src/main/scala/xiangshan/backend/Scheduler.scala
src/main/scala/xiangshan/backend/Scheduler.scala
+0
-6
src/main/scala/xiangshan/backend/exu/ExeUnit.scala
src/main/scala/xiangshan/backend/exu/ExeUnit.scala
+0
-1
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+0
-2
src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
+7
-49
src/main/scala/xiangshan/backend/issue/DataArray.scala
src/main/scala/xiangshan/backend/issue/DataArray.scala
+3
-18
src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
...cala/xiangshan/backend/issue/ReservationStationBase.scala
+0
-5
src/main/scala/xiangshan/backend/issue/ReservationStationFMA.scala
...scala/xiangshan/backend/issue/ReservationStationFMA.scala
+0
-104
src/main/scala/xiangshan/backend/issue/StatusArray.scala
src/main/scala/xiangshan/backend/issue/StatusArray.scala
+2
-10
未找到文件。
src/main/scala/xiangshan/backend/ExuBlock.scala
浏览文件 @
c15d13ad
...
@@ -96,9 +96,6 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
...
@@ -96,9 +96,6 @@ class ExuBlockImp(outer: ExuBlock)(implicit p: Parameters) extends LazyModuleImp
// the scheduler issues instructions to function units
// the scheduler issues instructions to function units
scheduler
.
io
.
issue
<>
fuBlock
.
io
.
issue
++
io
.
issue
.
getOrElse
(
Seq
())
scheduler
.
io
.
issue
<>
fuBlock
.
io
.
issue
++
io
.
issue
.
getOrElse
(
Seq
())
if
(
scheduler
.
io
.
fmaMid
.
isDefined
)
{
scheduler
.
io
.
fmaMid
.
get
<>
fuBlock
.
io
.
fmaMid
.
get
}
// IO for the function units
// IO for the function units
fuBlock
.
io
.
redirect
<>
io
.
redirect
fuBlock
.
io
.
redirect
<>
io
.
redirect
...
...
src/main/scala/xiangshan/backend/FUBlock.scala
浏览文件 @
c15d13ad
...
@@ -24,7 +24,6 @@ import utils._
...
@@ -24,7 +24,6 @@ import utils._
import
xiangshan._
import
xiangshan._
import
xiangshan.backend.exu._
import
xiangshan.backend.exu._
import
xiangshan.backend.fu.CSRFileIO
import
xiangshan.backend.fu.CSRFileIO
import
xiangshan.backend.fu.fpu.FMAMidResultIO
class
WakeUpBundle
(
numFast
:
Int
,
numSlow
:
Int
)(
implicit
p
:
Parameters
)
extends
XSBundle
{
class
WakeUpBundle
(
numFast
:
Int
,
numSlow
:
Int
)(
implicit
p
:
Parameters
)
extends
XSBundle
{
val
fastUops
=
Vec
(
numFast
,
Flipped
(
ValidIO
(
new
MicroOp
)))
val
fastUops
=
Vec
(
numFast
,
Flipped
(
ValidIO
(
new
MicroOp
)))
...
@@ -58,7 +57,6 @@ class FUBlock(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) extends XS
...
@@ -58,7 +57,6 @@ class FUBlock(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) extends XS
val
writeback
=
Vec
(
numIn
,
DecoupledIO
(
new
ExuOutput
))
val
writeback
=
Vec
(
numIn
,
DecoupledIO
(
new
ExuOutput
))
// misc
// misc
val
extra
=
new
FUBlockExtraIO
(
configs
)
val
extra
=
new
FUBlockExtraIO
(
configs
)
val
fmaMid
=
if
(
numFma
>
0
)
Some
(
Vec
(
numFma
,
new
FMAMidResultIO
))
else
None
})
})
val
exuDefs
=
configs
.
map
(
_
.
_1
).
map
(
ExeUnitDef
(
_
))
val
exuDefs
=
configs
.
map
(
_
.
_1
).
map
(
ExeUnitDef
(
_
))
...
@@ -100,10 +98,6 @@ class FUBlock(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) extends XS
...
@@ -100,10 +98,6 @@ class FUBlock(configs: Seq[(ExuConfig, Int)])(implicit p: Parameters) extends XS
}
}
}
}
if
(
io
.
fmaMid
.
isDefined
)
{
io
.
fmaMid
.
get
<>
exeUnits
.
map
(
_
.
fmaMid
).
filter
(
_
.
isDefined
).
map
(
_
.
get
)
}
for
((
iss
,
i
)
<-
io
.
issue
.
zipWithIndex
)
{
for
((
iss
,
i
)
<-
io
.
issue
.
zipWithIndex
)
{
XSPerfAccumulate
(
s
"issue_count_$i"
,
iss
.
fire
())
XSPerfAccumulate
(
s
"issue_count_$i"
,
iss
.
fire
())
}
}
...
...
src/main/scala/xiangshan/backend/Scheduler.scala
浏览文件 @
c15d13ad
...
@@ -26,7 +26,6 @@ import xiangshan._
...
@@ -26,7 +26,6 @@ import xiangshan._
import
xiangshan.backend.dispatch.Dispatch2Rs
import
xiangshan.backend.dispatch.Dispatch2Rs
import
xiangshan.backend.exu.ExuConfig
import
xiangshan.backend.exu.ExuConfig
import
xiangshan.backend.fu.FuConfig
import
xiangshan.backend.fu.FuConfig
import
xiangshan.backend.fu.fpu.FMAMidResultIO
import
xiangshan.backend.issue.
{
BaseReservationStationWrapper
,
RSParams
,
RSMod
}
import
xiangshan.backend.issue.
{
BaseReservationStationWrapper
,
RSParams
,
RSMod
}
import
xiangshan.backend.regfile.
{
Regfile
,
RfReadPort
}
import
xiangshan.backend.regfile.
{
Regfile
,
RfReadPort
}
import
xiangshan.backend.rename.
{
BusyTable
,
BusyTableReadIO
}
import
xiangshan.backend.rename.
{
BusyTable
,
BusyTableReadIO
}
...
@@ -311,7 +310,6 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
...
@@ -311,7 +310,6 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
val
fastUopIn
=
Vec
(
intRfWritePorts
+
fpRfWritePorts
,
Flipped
(
ValidIO
(
new
MicroOp
)))
val
fastUopIn
=
Vec
(
intRfWritePorts
+
fpRfWritePorts
,
Flipped
(
ValidIO
(
new
MicroOp
)))
// misc ports
// misc ports
val
extra
=
new
SchedulerExtraIO
val
extra
=
new
SchedulerExtraIO
val
fmaMid
=
if
(
numFma
>
0
)
Some
(
Vec
(
numFma
,
Flipped
(
new
FMAMidResultIO
)))
else
None
})
})
// To reduce fanout, we add registers here for redirect.
// To reduce fanout, we add registers here for redirect.
...
@@ -375,10 +373,6 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
...
@@ -375,10 +373,6 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
}
else
None
}
else
None
val
allocate
=
dispatch2
.
flatMap
(
_
.
io
.
out
)
val
allocate
=
dispatch2
.
flatMap
(
_
.
io
.
out
)
if
(
io
.
fmaMid
.
isDefined
)
{
io
.
fmaMid
.
get
<>
outer
.
reservationStations
.
filter
(
_
.
params
.
isFMA
).
flatMap
(
_
.
module
.
extra
.
fmaMid
)
}
// extract each dispatch-rs port's psrc
// extract each dispatch-rs port's psrc
def
extractReadRf
(
numRead
:
Seq
[
Int
])
:
Seq
[
UInt
]
=
{
def
extractReadRf
(
numRead
:
Seq
[
Int
])
:
Seq
[
UInt
]
=
{
require
(
numRead
.
length
==
allocate
.
length
)
require
(
numRead
.
length
==
allocate
.
length
)
...
...
src/main/scala/xiangshan/backend/exu/ExeUnit.scala
浏览文件 @
c15d13ad
...
@@ -94,7 +94,6 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) {
...
@@ -94,7 +94,6 @@ class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) {
val
fmaModules
=
functionUnits
.
filter
(
_
.
isInstanceOf
[
FMA
]).
map
(
_
.
asInstanceOf
[
FMA
])
val
fmaModules
=
functionUnits
.
filter
(
_
.
isInstanceOf
[
FMA
]).
map
(
_
.
asInstanceOf
[
FMA
])
if
(
fmaModules
.
nonEmpty
)
{
if
(
fmaModules
.
nonEmpty
)
{
require
(
fmaModules
.
length
==
1
)
require
(
fmaModules
.
length
==
1
)
fmaModules
.
head
.
midResult
<>
fmaMid
.
get
}
}
if
(
config
.
readIntRf
)
{
if
(
config
.
readIntRf
)
{
...
...
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
c15d13ad
...
@@ -23,7 +23,6 @@ import chisel3.util._
...
@@ -23,7 +23,6 @@ import chisel3.util._
import
utils.XSPerfAccumulate
import
utils.XSPerfAccumulate
import
xiangshan._
import
xiangshan._
import
xiangshan.backend.fu._
import
xiangshan.backend.fu._
import
xiangshan.backend.fu.fpu.FMAMidResultIO
case
class
ExuParameters
case
class
ExuParameters
(
(
...
@@ -123,7 +122,6 @@ abstract class Exu(cfg: ExuConfig)(implicit p: Parameters) extends XSModule {
...
@@ -123,7 +122,6 @@ abstract class Exu(cfg: ExuConfig)(implicit p: Parameters) extends XSModule {
@public
val
csrio
=
if
(
config
==
JumpCSRExeUnitCfg
)
Some
(
IO
(
new
CSRFileIO
))
else
None
@public
val
csrio
=
if
(
config
==
JumpCSRExeUnitCfg
)
Some
(
IO
(
new
CSRFileIO
))
else
None
@public
val
fenceio
=
if
(
config
==
JumpCSRExeUnitCfg
)
Some
(
IO
(
new
FenceIO
))
else
None
@public
val
fenceio
=
if
(
config
==
JumpCSRExeUnitCfg
)
Some
(
IO
(
new
FenceIO
))
else
None
@public
val
frm
=
if
(
config
==
FmacExeUnitCfg
||
config
==
FmiscExeUnitCfg
)
Some
(
IO
(
Input
(
UInt
(
3.
W
))))
else
None
@public
val
frm
=
if
(
config
==
FmacExeUnitCfg
||
config
==
FmiscExeUnitCfg
)
Some
(
IO
(
Input
(
UInt
(
3.
W
))))
else
None
@public
val
fmaMid
=
if
(
config
==
FmacExeUnitCfg
)
Some
(
IO
(
new
FMAMidResultIO
))
else
None
val
functionUnits
=
config
.
fuConfigs
.
map
(
cfg
=>
{
val
functionUnits
=
config
.
fuConfigs
.
map
(
cfg
=>
{
val
mod
=
Module
(
cfg
.
fuGen
(
p
))
val
mod
=
Module
(
cfg
.
fuGen
(
p
))
...
...
src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
浏览文件 @
c15d13ad
...
@@ -158,34 +158,7 @@ class FADD_pipe(val addLat: Int = 2)(implicit p: Parameters) extends FPUPipeline
...
@@ -158,34 +158,7 @@ class FADD_pipe(val addLat: Int = 2)(implicit p: Parameters) extends FPUPipeline
fflags
:=
Mux1H
(
outSel
,
s2
.
map
(
_
.
io
.
fflags
))
fflags
:=
Mux1H
(
outSel
,
s2
.
map
(
_
.
io
.
fflags
))
}
}
class
FMAMidResult
extends
FMULToFADD
(
FPU
.
ftypes
.
last
.
expWidth
,
FPU
.
ftypes
.
last
.
precision
)
{
def
toFloat
:
FMULToFADD
=
{
val
floatMidResult
=
Wire
(
new
FMULToFADD
(
FPU
.
ftypes
.
head
.
expWidth
,
FPU
.
ftypes
.
head
.
precision
))
floatMidResult
.
fp_prod
.
sign
:=
fp_prod
.
sign
floatMidResult
.
fp_prod
.
exp
:=
fp_prod
.
exp
floatMidResult
.
fp_prod
.
sig
:=
fp_prod
.
sig
floatMidResult
.
inter_flags
:=
inter_flags
floatMidResult
}
def
fromFloat
(
float
:
FMULToFADD
)
:
FMULToFADD
=
{
fp_prod
.
sign
:=
float
.
fp_prod
.
sign
fp_prod
.
exp
:=
float
.
fp_prod
.
exp
fp_prod
.
sig
:=
float
.
fp_prod
.
sig
inter_flags
:=
float
.
inter_flags
this
}
}
class
FMAMidResultIO
extends
Bundle
{
val
in
=
Flipped
(
ValidIO
(
new
FMAMidResult
))
val
out
=
ValidIO
(
new
FMAMidResult
)
val
waitForAdd
=
Input
(
Bool
())
}
class
FMA
(
implicit
p
:
Parameters
)
extends
FPUSubModule
{
class
FMA
(
implicit
p
:
Parameters
)
extends
FPUSubModule
{
val
midResult
=
IO
(
new
FMAMidResultIO
)
override
val
dataModule
=
null
override
val
dataModule
=
null
val
mul_pipe
=
Module
(
new
FMUL_pipe
())
val
mul_pipe
=
Module
(
new
FMUL_pipe
())
...
@@ -200,38 +173,26 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
...
@@ -200,38 +173,26 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
val
fpCtrl
=
io
.
in
.
bits
.
uop
.
ctrl
.
fpu
val
fpCtrl
=
io
.
in
.
bits
.
uop
.
ctrl
.
fpu
mul_pipe
.
io
.
in
<>
io
.
in
mul_pipe
.
io
.
in
<>
io
.
in
mul_pipe
.
io
.
in
.
valid
:=
io
.
in
.
valid
&&
!
fpCtrl
.
isAddSub
&&
!
midResult
.
in
.
valid
mul_pipe
.
io
.
in
.
valid
:=
io
.
in
.
valid
&&
!
fpCtrl
.
isAddSub
// For better timing, we let out.valid be true even if it's flushed.
// For better timing, we let out.valid be true even if it's flushed.
val
waitAddOperand
=
RegEnable
(
midResult
.
waitForAdd
,
!
mul_pipe
.
io
.
out
.
valid
||
mul_pipe
.
io
.
out
.
ready
)
val
isFMA
=
mul_pipe
.
io
.
out
.
valid
&&
mul_pipe
.
io
.
out
.
bits
.
uop
.
ctrl
.
fpu
.
ren3
val
isFMA
=
mul_pipe
.
io
.
out
.
valid
&&
mul_pipe
.
io
.
out
.
bits
.
uop
.
ctrl
.
fpu
.
ren3
&&
!
waitAddOperand
// However, when sending instructions to add_pipe, we need to determine whether it's flushed.
// However, when sending instructions to add_pipe, we need to determine whether it's flushed.
val
mulFlushed
=
mul_pipe
.
io
.
out
.
bits
.
uop
.
robIdx
.
needFlush
(
io
.
redirectIn
)
val
mulFlushed
=
mul_pipe
.
io
.
out
.
bits
.
uop
.
robIdx
.
needFlush
(
io
.
redirectIn
)
val
isFMAReg
=
RegNext
(
isFMA
&&
!
mulFlushed
)
val
isFMAReg
=
RegNext
(
isFMA
&&
!
mulFlushed
)
add_pipe
.
mulToAdd
<>
mul_pipe
.
toAdd
add_pipe
.
mulToAdd
<>
mul_pipe
.
toAdd
midResult
.
out
.
valid
:=
RegNext
(
mul_pipe
.
io
.
out
.
valid
&&
waitAddOperand
&&
!
mulFlushed
)
midResult
.
out
.
bits
:=
mul_pipe
.
toAdd
.
getDouble
when
(
RegNext
(
mul_pipe
.
io
.
out
.
bits
.
uop
.
ctrl
.
fpu
.
typeTagIn
===
FPU
.
S
))
{
midResult
.
out
.
bits
.
fromFloat
(
mul_pipe
.
toAdd
.
getFloat
)
}
when
(
midResult
.
in
.
valid
&&
!
isFMAReg
)
{
add_pipe
.
mulToAdd
.
getDouble
:=
midResult
.
in
.
bits
add_pipe
.
mulToAdd
.
getFloat
:=
midResult
.
in
.
bits
.
toFloat
add_pipe
.
mulToAdd
.
addend
:=
io
.
in
.
bits
.
src
(
2
)
add_pipe
.
mulToAdd
.
uop
:=
io
.
in
.
bits
.
uop
}
// For FADD, it accepts instructions from io.in and FMUL.
// For FADD, it accepts instructions from io.in and FMUL.
// When FMUL gives an FMA, FADD accepts this instead of io.in.
// When FMUL gives an FMA, FADD accepts this instead of io.in.
// Since FADD gets FMUL data from add_pipe.mulToAdd, only uop needs Mux.
// Since FADD gets FMUL data from add_pipe.mulToAdd, only uop needs Mux.
add_pipe
.
io
.
in
.
valid
:=
io
.
in
.
valid
&&
(
fpCtrl
.
isAddSub
||
midResult
.
in
.
valid
)
||
isFMAReg
add_pipe
.
io
.
in
.
valid
:=
io
.
in
.
valid
&&
fpCtrl
.
isAddSub
||
isFMAReg
add_pipe
.
io
.
in
.
bits
.
src
:=
io
.
in
.
bits
.
src
add_pipe
.
io
.
in
.
bits
.
src
:=
io
.
in
.
bits
.
src
add_pipe
.
io
.
in
.
bits
.
uop
:=
Mux
(
isFMAReg
,
add_pipe
.
mulToAdd
.
uop
,
io
.
in
.
bits
.
uop
)
add_pipe
.
io
.
in
.
bits
.
uop
:=
Mux
(
isFMAReg
,
add_pipe
.
mulToAdd
.
uop
,
io
.
in
.
bits
.
uop
)
add_pipe
.
isFMA
:=
i
o
.
in
.
valid
&&
midResult
.
in
.
valid
||
i
sFMAReg
add_pipe
.
isFMA
:=
isFMAReg
// When the in uop is Add/Sub, we check FADD, otherwise fmul is checked.
// When the in uop is Add/Sub, we check FADD, otherwise fmul is checked.
io
.
in
.
ready
:=
Mux
(
fpCtrl
.
isAddSub
||
midResult
.
in
.
valid
,
io
.
in
.
ready
:=
Mux
(
fpCtrl
.
isAddSub
,
!
isFMAReg
&&
add_pipe
.
io
.
in
.
ready
,
!
isFMAReg
&&
add_pipe
.
io
.
in
.
ready
,
mul_pipe
.
io
.
in
.
ready
mul_pipe
.
io
.
in
.
ready
)
)
...
@@ -240,7 +201,7 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
...
@@ -240,7 +201,7 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
// (1) It always accept FMA from FADD (if an FMA wants FMUL, it's never blocked).
// (1) It always accept FMA from FADD (if an FMA wants FMUL, it's never blocked).
// (2) It has lower writeback arbitration priority than FADD (and may be blocked when FMUL.out.valid).
// (2) It has lower writeback arbitration priority than FADD (and may be blocked when FMUL.out.valid).
XSError
(
isFMA
&&
!
add_pipe
.
io
.
in
.
ready
,
"FMA should not be blocked\n"
)
XSError
(
isFMA
&&
!
add_pipe
.
io
.
in
.
ready
,
"FMA should not be blocked\n"
)
mul_pipe
.
io
.
out
.
ready
:=
isFMA
||
(
io
.
out
.
ready
&&
!
add_pipe
.
io
.
out
.
valid
)
||
waitAddOperand
mul_pipe
.
io
.
out
.
ready
:=
isFMA
||
(
io
.
out
.
ready
&&
!
add_pipe
.
io
.
out
.
valid
)
add_pipe
.
io
.
out
.
ready
:=
io
.
out
.
ready
add_pipe
.
io
.
out
.
ready
:=
io
.
out
.
ready
io
.
out
.
bits
.
uop
:=
Mux
(
add_pipe
.
io
.
out
.
valid
,
io
.
out
.
bits
.
uop
:=
Mux
(
add_pipe
.
io
.
out
.
valid
,
...
@@ -255,8 +216,5 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
...
@@ -255,8 +216,5 @@ class FMA(implicit p: Parameters) extends FPUSubModule {
add_pipe
.
fflags
,
add_pipe
.
fflags
,
mul_pipe
.
fflags
mul_pipe
.
fflags
)
)
io
.
out
.
valid
:=
add_pipe
.
io
.
out
.
valid
||
(
mul_pipe
.
io
.
out
.
valid
&&
!
isFMA
&&
!
waitAddOperand
)
io
.
out
.
valid
:=
add_pipe
.
io
.
out
.
valid
||
(
mul_pipe
.
io
.
out
.
valid
&&
!
isFMA
)
XSPerfAccumulate
(
"fma_partial_issue_fire"
,
io
.
in
.
fire
&&
midResult
.
waitForAdd
)
XSPerfAccumulate
(
"fma_mid_result_in_fire"
,
io
.
in
.
fire
&&
midResult
.
in
.
valid
)
}
}
src/main/scala/xiangshan/backend/issue/DataArray.scala
浏览文件 @
c15d13ad
...
@@ -53,7 +53,6 @@ class DataArrayIO(params: RSParams)(implicit p: Parameters) extends XSBundle {
...
@@ -53,7 +53,6 @@ class DataArrayIO(params: RSParams)(implicit p: Parameters) extends XSBundle {
val
write
=
Vec
(
params
.
numEnq
,
new
DataArrayWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
val
write
=
Vec
(
params
.
numEnq
,
new
DataArrayWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
val
multiWrite
=
Vec
(
params
.
numWakeup
,
new
DataArrayMultiWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
val
multiWrite
=
Vec
(
params
.
numWakeup
,
new
DataArrayMultiWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
val
delayedWrite
=
if
(
params
.
delayedSrc
)
Vec
(
params
.
numEnq
,
new
DataArrayDelayedWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
else
null
val
delayedWrite
=
if
(
params
.
delayedSrc
)
Vec
(
params
.
numEnq
,
new
DataArrayDelayedWriteIO
(
params
.
numEntries
,
params
.
numSrc
,
params
.
dataBits
))
else
null
val
partialWrite
=
if
(
params
.
hasMidState
)
Vec
(
params
.
numDeq
,
new
DataArrayWriteIO
(
params
.
numEntries
,
params
.
numSrc
-
1
,
params
.
dataBits
))
else
null
}
}
class
DataArray
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
XSModule
{
class
DataArray
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
XSModule
{
...
@@ -64,13 +63,9 @@ class DataArray(params: RSParams)(implicit p: Parameters) extends XSModule {
...
@@ -64,13 +63,9 @@ class DataArray(params: RSParams)(implicit p: Parameters) extends XSModule {
val
delayedWaddr
=
if
(
params
.
delayedSrc
)
io
.
delayedWrite
.
map
(
_
.
addr
)
else
Seq
()
val
delayedWaddr
=
if
(
params
.
delayedSrc
)
io
.
delayedWrite
.
map
(
_
.
addr
)
else
Seq
()
val
delayedWdata
=
if
(
params
.
delayedSrc
)
io
.
delayedWrite
.
map
(
_
.
data
(
i
))
else
Seq
()
val
delayedWdata
=
if
(
params
.
delayedSrc
)
io
.
delayedWrite
.
map
(
_
.
data
(
i
))
else
Seq
()
val
partialWen
=
if
(
i
<
2
&&
params
.
hasMidState
)
io
.
partialWrite
.
map
(
w
=>
RegNext
(
w
.
enable
))
else
Seq
()
val
wen
=
io
.
write
.
map
(
w
=>
w
.
enable
&&
w
.
mask
(
i
))
++
io
.
multiWrite
.
map
(
_
.
enable
)
++
delayedWen
val
partialWaddr
=
if
(
i
<
2
&&
params
.
hasMidState
)
io
.
partialWrite
.
map
(
w
=>
RegEnable
(
w
.
addr
,
w
.
enable
))
else
Seq
()
val
waddr
=
io
.
write
.
map
(
_
.
addr
)
++
io
.
multiWrite
.
map
(
_
.
addr
(
i
))
++
delayedWaddr
val
partialWdata
=
if
(
i
<
2
&&
params
.
hasMidState
)
io
.
partialWrite
.
map
(
w
=>
RegEnable
(
w
.
data
(
i
),
w
.
enable
))
else
Seq
()
val
wdata
=
io
.
write
.
map
(
_
.
data
(
i
))
++
io
.
multiWrite
.
map
(
_
.
data
)
++
delayedWdata
val
wen
=
io
.
write
.
map
(
w
=>
w
.
enable
&&
w
.
mask
(
i
))
++
io
.
multiWrite
.
map
(
_
.
enable
)
++
delayedWen
++
partialWen
val
waddr
=
io
.
write
.
map
(
_
.
addr
)
++
io
.
multiWrite
.
map
(
_
.
addr
(
i
))
++
delayedWaddr
++
partialWaddr
val
wdata
=
io
.
write
.
map
(
_
.
data
(
i
))
++
io
.
multiWrite
.
map
(
_
.
data
)
++
delayedWdata
++
partialWdata
val
dataModule
=
Module
(
new
AsyncRawDataModuleTemplate
(
UInt
(
params
.
dataBits
.
W
),
params
.
numEntries
,
io
.
read
.
length
,
wen
.
length
))
val
dataModule
=
Module
(
new
AsyncRawDataModuleTemplate
(
UInt
(
params
.
dataBits
.
W
),
params
.
numEntries
,
io
.
read
.
length
,
wen
.
length
))
dataModule
.
io
.
rvec
:=
VecInit
(
io
.
read
.
map
(
_
.
addr
))
dataModule
.
io
.
rvec
:=
VecInit
(
io
.
read
.
map
(
_
.
addr
))
...
@@ -79,16 +74,6 @@ class DataArray(params: RSParams)(implicit p: Parameters) extends XSModule {
...
@@ -79,16 +74,6 @@ class DataArray(params: RSParams)(implicit p: Parameters) extends XSModule {
dataModule
.
io
.
wvec
:=
waddr
dataModule
.
io
.
wvec
:=
waddr
dataModule
.
io
.
wdata
:=
wdata
dataModule
.
io
.
wdata
:=
wdata
if
(
i
<
2
&&
params
.
hasMidState
)
{
for
(
r
<-
io
.
read
)
{
val
addr_match
=
partialWaddr
.
map
(
addr
=>
(
addr
&
r
.
addr
).
asUInt
.
orR
)
val
bypass
=
partialWen
.
zip
(
addr_match
).
map
(
p
=>
p
.
_1
&&
p
.
_2
)
when
(
VecInit
(
bypass
).
asUInt
.
orR
)
{
r
.
data
(
i
)
:=
Mux1H
(
bypass
,
partialWdata
)
}
}
}
for
(
i
<-
0
until
params
.
numEntries
)
{
for
(
i
<-
0
until
params
.
numEntries
)
{
val
w
=
VecInit
(
wen
.
indices
.
map
(
j
=>
dataModule
.
io
.
wen
(
j
)
&&
dataModule
.
io
.
wvec
(
j
)(
i
)))
val
w
=
VecInit
(
wen
.
indices
.
map
(
j
=>
dataModule
.
io
.
wen
(
j
)
&&
dataModule
.
io
.
wvec
(
j
)(
i
)))
XSError
(
RegNext
(
PopCount
(
w
)
>
1.
U
),
s
"why not OH $i?"
)
XSError
(
RegNext
(
PopCount
(
w
)
>
1.
U
),
s
"why not OH $i?"
)
...
...
src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
浏览文件 @
c15d13ad
...
@@ -24,7 +24,6 @@ import utils._
...
@@ -24,7 +24,6 @@ import utils._
import
xiangshan._
import
xiangshan._
import
xiangshan.backend.exu.ExuConfig
import
xiangshan.backend.exu.ExuConfig
import
xiangshan.backend.fu.FuConfig
import
xiangshan.backend.fu.FuConfig
import
xiangshan.backend.fu.fpu.FMAMidResultIO
import
xiangshan.mem.
{
MemWaitUpdateReq
,
SqPtr
}
import
xiangshan.mem.
{
MemWaitUpdateReq
,
SqPtr
}
import
scala.math.max
import
scala.math.max
...
@@ -69,7 +68,6 @@ case class RSParams
...
@@ -69,7 +68,6 @@ case class RSParams
def
indexWidth
:
Int
=
log2Up
(
numEntries
)
def
indexWidth
:
Int
=
log2Up
(
numEntries
)
// oldestFirst: (Enable_or_not, Need_balance, Victim_index)
// oldestFirst: (Enable_or_not, Need_balance, Victim_index)
def
oldestFirst
:
(
Boolean
,
Boolean
,
Int
)
=
(
true
,
false
,
0
)
def
oldestFirst
:
(
Boolean
,
Boolean
,
Int
)
=
(
true
,
false
,
0
)
def
hasMidState
:
Boolean
=
exuCfg
.
get
==
FmacExeUnitCfg
def
delayedSrc
:
Boolean
=
exuCfg
.
get
==
StdExeUnitCfg
def
delayedSrc
:
Boolean
=
exuCfg
.
get
==
StdExeUnitCfg
def
needBalance
:
Boolean
=
exuCfg
.
get
.
needLoadBalance
&&
exuCfg
.
get
!=
LdExeUnitCfg
def
needBalance
:
Boolean
=
exuCfg
.
get
.
needLoadBalance
&&
exuCfg
.
get
!=
LdExeUnitCfg
def
numSelect
:
Int
=
numDeq
+
numEnq
+
(
if
(
oldestFirst
.
_1
)
1
else
0
)
def
numSelect
:
Int
=
numDeq
+
numEnq
+
(
if
(
oldestFirst
.
_1
)
1
else
0
)
...
@@ -241,7 +239,6 @@ class RSExtraIO(params: RSParams)(implicit p: Parameters) extends XSBundle {
...
@@ -241,7 +239,6 @@ class RSExtraIO(params: RSParams)(implicit p: Parameters) extends XSBundle {
val
stIssue
=
Flipped
(
Vec
(
exuParameters
.
StuCnt
,
ValidIO
(
new
ExuInput
)))
val
stIssue
=
Flipped
(
Vec
(
exuParameters
.
StuCnt
,
ValidIO
(
new
ExuInput
)))
val
memWaitUpdateReq
=
Flipped
(
new
MemWaitUpdateReq
)
val
memWaitUpdateReq
=
Flipped
(
new
MemWaitUpdateReq
)
}
}
val
fmaMid
=
Vec
(
params
.
numDeq
,
Flipped
(
new
FMAMidResultIO
))
}
}
class
BaseReservationStation
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
RSModule
class
BaseReservationStation
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
RSModule
...
@@ -429,7 +426,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -429,7 +426,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
for
(
j
<-
0
until
params
.
numSrc
)
{
for
(
j
<-
0
until
params
.
numSrc
)
{
statusUpdate
.
data
.
srcState
(
j
)
:=
uop
.
bits
.
srcIsReady
(
j
)
||
s1_enqWakeup
(
i
)(
j
).
asUInt
.
orR
||
s1_fastWakeup
(
i
)(
j
).
asUInt
.
orR
statusUpdate
.
data
.
srcState
(
j
)
:=
uop
.
bits
.
srcIsReady
(
j
)
||
s1_enqWakeup
(
i
)(
j
).
asUInt
.
orR
||
s1_fastWakeup
(
i
)(
j
).
asUInt
.
orR
}
}
statusUpdate
.
data
.
midState
:=
false
.
B
statusUpdate
.
data
.
psrc
:=
uop
.
bits
.
psrc
.
take
(
params
.
numSrc
)
statusUpdate
.
data
.
psrc
:=
uop
.
bits
.
psrc
.
take
(
params
.
numSrc
)
statusUpdate
.
data
.
srcType
:=
uop
.
bits
.
ctrl
.
srcType
.
take
(
params
.
numSrc
)
statusUpdate
.
data
.
srcType
:=
uop
.
bits
.
ctrl
.
srcType
.
take
(
params
.
numSrc
)
statusUpdate
.
data
.
robIdx
:=
uop
.
bits
.
robIdx
statusUpdate
.
data
.
robIdx
:=
uop
.
bits
.
robIdx
...
@@ -539,7 +535,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -539,7 +535,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
statusArray
.
io
.
deqResp
.
last
.
bits
.
success
:=
ParallelMux
(
s1_issue_oldest
,
s2_deq
.
map
(
_
.
ready
))
statusArray
.
io
.
deqResp
.
last
.
bits
.
success
:=
ParallelMux
(
s1_issue_oldest
,
s2_deq
.
map
(
_
.
ready
))
statusArray
.
io
.
deqResp
.
last
.
bits
.
resptype
:=
DontCare
statusArray
.
io
.
deqResp
.
last
.
bits
.
resptype
:=
DontCare
statusArray
.
io
.
deqResp
.
last
.
bits
.
dataInvalidSqIdx
:=
DontCare
statusArray
.
io
.
deqResp
.
last
.
bits
.
dataInvalidSqIdx
:=
DontCare
statusArray
.
io
.
updateMidState
:=
0.
U
// select whether the source is from (whether slowPorts, regfile or imm)
// select whether the source is from (whether slowPorts, regfile or imm)
// for read-after-issue, it's done over the selected uop
// for read-after-issue, it's done over the selected uop
...
...
src/main/scala/xiangshan/backend/issue/ReservationStationFMA.scala
浏览文件 @
c15d13ad
...
@@ -31,111 +31,7 @@ class FMARSWrapper(modGen: RSMod)(implicit p: Parameters) extends BaseReservatio
...
@@ -31,111 +31,7 @@ class FMARSWrapper(modGen: RSMod)(implicit p: Parameters) extends BaseReservatio
}
}
class
FMARSImp
(
params
:
RSParams
,
wrapper
:
FMARSWrapper
)
extends
BaseReservationStationImp
(
params
,
wrapper
)
{
class
FMARSImp
(
params
:
RSParams
,
wrapper
:
FMARSWrapper
)
extends
BaseReservationStationImp
(
params
,
wrapper
)
{
extra
.
fmaMid
<>
rs
.
flatMap
(
_
.
extra
.
fmaMid
)
}
}
class
FMARS
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
BaseReservationStation
(
params
)
{
class
FMARS
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
BaseReservationStation
(
params
)
{
for
(
i
<-
0
until
params
.
numDeq
)
{
if
(
params
.
hasMidState
)
{
extra
.
fmaMid
(
i
).
waitForAdd
:=
!
s2_all_src_ready
(
i
)
extra
.
fmaMid
(
i
).
in
.
valid
:=
!
s2_first_issue
(
i
)
XSPerfAccumulate
(
s
"fma_partial2_issue_$i"
,
io
.
deq
(
i
).
fire
&&
extra
.
fmaMid
(
i
).
waitForAdd
)
XSPerfAccumulate
(
s
"fma_final_issue_$i"
,
io
.
deq
(
i
).
fire
&&
extra
.
fmaMid
(
i
).
in
.
valid
)
}
}
// For FMA instrutions whose third operand is not ready, once they are successfully issued (T0),
// the FMUL intermediate result will be ready in two clock cycles (T2).
// If the third operand is ready at T2, this instruction will be selected in T3 and issued at T4.
// Note that at cycle T4, FMUL finishes as well and it is able to proceed to FADD.
// Thus, we can set the midState to true two cycles earlier at T0 and forward the result if possible.
val
midFinished2
=
extra
.
fmaMid
.
zip
(
io
.
deq
).
map
(
x
=>
x
.
_1
.
waitForAdd
&&
x
.
_2
.
fire
)
val
updateMid
=
ParallelMux
(
midFinished2
,
s2_issuePtrOH
)
statusArray
.
io
.
updateMidState
:=
updateMid
// FMUL intermediate results are ready in two cycles
val
midFinished2T0
=
midFinished2
.
zip
(
s2_deq
).
map
{
case
(
v
,
deq
)
=>
// However, it may be flushed by redirect at T0.
// If flushed at T0, new instruction enters at T1 and writes the entry at T2.
// This is a rare case because usually instructions enter RS in-order,
// unless dispatch2 is blocked.
v
&&
!
deq
.
bits
.
uop
.
robIdx
.
needFlush
(
io
.
redirect
)
}
val
midIssuePtrOHT1
=
midFinished2T0
.
zip
(
s2_issuePtrOH
).
map
(
x
=>
RegEnable
(
x
.
_2
,
x
.
_1
))
val
midIssuePtrT1
=
midFinished2T0
.
zip
(
s2_issuePtr
).
map
(
x
=>
RegEnable
(
x
.
_2
,
x
.
_1
))
val
midFinished2T1
=
midFinished2T0
.
map
(
v
=>
RegNext
(
v
))
// No flush here: the fma may dequeue at this stage.
// If cancelled at T1, data written at T2. However, new instruction writes at least at T3.
val
midIssuePtrOHT2
=
midFinished2T1
.
zip
(
midIssuePtrOHT1
).
map
(
x
=>
RegEnable
(
x
.
_2
,
x
.
_1
))
val
midIssuePtrT2
=
midFinished2T1
.
zip
(
midIssuePtrT1
).
map
(
x
=>
RegEnable
(
x
.
_2
,
x
.
_1
))
val
midFinished2T2
=
midFinished2T1
.
map
(
v
=>
RegNext
(
v
))
for
(
i
<-
0
until
params
.
numDeq
)
{
dataArray
.
io
.
partialWrite
(
i
).
enable
:=
midFinished2T2
(
i
)
dataArray
.
io
.
partialWrite
(
i
).
mask
:=
DontCare
dataArray
.
io
.
partialWrite
(
i
).
addr
:=
midIssuePtrOHT2
(
i
)
val
writeData
=
extra
.
fmaMid
(
i
).
out
.
bits
.
asUInt
require
(
writeData
.
getWidth
<=
2
*
params
.
dataBits
,
s
"why ${writeData.getWidth}???"
)
require
(
writeData
.
getWidth
>
params
.
dataBits
,
s
"why ${writeData.getWidth}???"
)
dataArray
.
io
.
partialWrite
(
i
).
data
(
0
)
:=
writeData
(
params
.
dataBits
-
1
,
0
)
dataArray
.
io
.
partialWrite
(
i
).
data
(
1
)
:=
writeData
(
writeData
.
getWidth
-
1
,
params
.
dataBits
)
val
readData
=
Cat
(
io
.
deq
(
i
).
bits
.
src
(
1
),
io
.
deq
(
i
).
bits
.
src
(
0
))
extra
.
fmaMid
(
i
).
in
.
bits
:=
readData
.
asTypeOf
(
extra
.
fmaMid
(
i
).
in
.
bits
.
cloneType
)
}
// How to forward intermediate results:
// (1) T0 issued FMA is selected at T1 and issued at T2: forward from FMUL results
// NOTE: In this case, this instruction has been issued and the entry is freed.
// Do NOT write data back to data array.
// (2) T0 issued FMA is selected at T2: RegNext FMUL result at the issue stage
// Thus, at issue stage:
// (1.1) If the instruction matches FMA/FMUL two cycles ealier, we issue it and it goes to FADD
// (1.2) If the instruction matches FMA/FMUL two cycles ealier and it's blocked, we need to hold the result
// At select stage: (2) bypass FMUL intermediate results from write ports if possible.
val
issuedAtT0
=
midFinished2T2
.
zip
(
midIssuePtrT2
)
for
(
i
<-
0
until
params
.
numDeq
)
{
// cond11: condition (1.1) from different issue ports
val
cond11
=
issuedAtT0
.
map
(
x
=>
x
.
_1
&&
x
.
_2
===
s2_issuePtr
(
i
))
for
((
c
,
j
)
<-
cond11
.
zipWithIndex
)
{
when
(
c
)
{
extra
.
fmaMid
(
i
).
in
.
bits
:=
extra
.
fmaMid
(
j
).
out
.
bits
// We should NOT write the intermediate result back to DataArray,
// when this entry has been selected and arrived at the issue stage.
// This entry may be allocated for new instructions from dispatch.
when
(
io
.
deq
(
i
).
valid
)
{
dataArray
.
io
.
partialWrite
(
j
).
enable
:=
false
.
B
}
}
}
val
cond11Issued
=
io
.
deq
(
i
).
fire
&&
extra
.
fmaMid
(
i
).
in
.
valid
&&
VecInit
(
cond11
).
asUInt
.
orR
XSPerfAccumulate
(
s
"fma_final_issue_cond11_$i"
,
cond11Issued
)
// cond12: blocked at the issue stage
val
cond12
=
cond11
.
map
(
_
&&
io
.
deq
(
i
).
valid
&&
!
io
.
deq
(
i
).
ready
)
val
hasCond12
=
VecInit
(
cond12
).
asUInt
.
orR
val
hasCond12Reg
=
RegInit
(
false
.
B
)
when
(
hasCond12
)
{
hasCond12Reg
:=
true
.
B
}.
elsewhen
(
io
.
deq
(
i
).
ready
)
{
hasCond12Reg
:=
false
.
B
}
when
(
hasCond12Reg
)
{
// TODO: remove these unnecessary registers (use pipeline registers instead)
extra
.
fmaMid
(
i
).
in
.
bits
:=
RegEnable
(
Mux1H
(
cond12
,
extra
.
fmaMid
.
map
(
_
.
out
.
bits
)),
hasCond12
)
}
val
cond12Issued
=
io
.
deq
(
i
).
fire
&&
extra
.
fmaMid
(
i
).
in
.
valid
&&
hasCond12Reg
XSPerfAccumulate
(
s
"fma_final_issue_cond12_$i"
,
cond12Issued
)
// cond2: selected at the select stage
val
cond2
=
issuedAtT0
.
map
(
x
=>
x
.
_1
&&
x
.
_2
===
s1_issuePtr
(
i
))
for
((
c
,
j
)
<-
cond2
.
zipWithIndex
)
{
when
(
c
)
{
s1_out
(
i
).
bits
.
src
(
0
)
:=
dataArray
.
io
.
partialWrite
(
j
).
data
(
0
)
s1_out
(
i
).
bits
.
src
(
1
)
:=
dataArray
.
io
.
partialWrite
(
j
).
data
(
1
)
}
}
val
cond2Selected
=
s1_out_fire
(
i
)
&&
VecInit
(
cond2
).
asUInt
.
orR
XSPerfAccumulate
(
s
"fma_final_selected_cond2_$i"
,
cond2Selected
)
}
allSrcReady
.
zip
(
s1_all_src_ready
).
map
(
a
=>
a
.
_1
:=
a
.
_2
)
allSrcReady1
.
zip
(
statusArray
.
io
.
update
.
map
(
_
.
data
.
allSrcReady
)).
map
(
a
=>
a
.
_1
:=
a
.
_2
)
allSrcReadyLast
:=
statusArray
.
io
.
allSrcReady
.
last
}
}
\ No newline at end of file
src/main/scala/xiangshan/backend/issue/StatusArray.scala
浏览文件 @
c15d13ad
...
@@ -40,7 +40,6 @@ class StatusEntry(params: RSParams)(implicit p: Parameters) extends XSBundle {
...
@@ -40,7 +40,6 @@ class StatusEntry(params: RSParams)(implicit p: Parameters) extends XSBundle {
val
blocked
=
Bool
()
val
blocked
=
Bool
()
val
credit
=
UInt
(
4.
W
)
val
credit
=
UInt
(
4.
W
)
val
srcState
=
Vec
(
params
.
numSrc
,
Bool
())
val
srcState
=
Vec
(
params
.
numSrc
,
Bool
())
val
midState
=
Bool
()
// data
// data
val
psrc
=
Vec
(
params
.
numSrc
,
UInt
(
params
.
dataIdBits
.
W
))
val
psrc
=
Vec
(
params
.
numSrc
,
UInt
(
params
.
dataIdBits
.
W
))
val
srcType
=
Vec
(
params
.
numSrc
,
SrcType
())
val
srcType
=
Vec
(
params
.
numSrc
,
SrcType
())
...
@@ -56,14 +55,11 @@ class StatusEntry(params: RSParams)(implicit p: Parameters) extends XSBundle {
...
@@ -56,14 +55,11 @@ class StatusEntry(params: RSParams)(implicit p: Parameters) extends XSBundle {
def
canIssue
:
Bool
=
{
def
canIssue
:
Bool
=
{
val
scheduledCond
=
if
(
params
.
needScheduledBit
)
!
scheduled
else
true
.
B
val
scheduledCond
=
if
(
params
.
needScheduledBit
)
!
scheduled
else
true
.
B
val
blockedCond
=
if
(
params
.
checkWaitBit
)
!
blocked
else
true
.
B
val
blockedCond
=
if
(
params
.
checkWaitBit
)
!
blocked
else
true
.
B
val
checkedSrcState
=
if
(
params
.
numSrc
>
2
)
srcState
.
take
(
2
)
else
srcState
srcState
.
asUInt
.
andR
&&
scheduledCond
&&
blockedCond
val
midStateReady
=
if
(
params
.
hasMidState
)
srcState
.
last
&&
midState
else
false
.
B
(
VecInit
(
checkedSrcState
).
asUInt
.
andR
&&
scheduledCond
||
midStateReady
)
&&
blockedCond
}
}
def
allSrcReady
:
Bool
=
{
def
allSrcReady
:
Bool
=
{
val
midStateReady
=
if
(
params
.
hasMidState
)
srcState
.
last
&&
midState
else
false
.
B
srcState
.
asUInt
.
andR
srcState
.
asUInt
.
andR
||
midStateReady
}
}
override
def
toPrintable
:
Printable
=
{
override
def
toPrintable
:
Printable
=
{
...
@@ -88,7 +84,6 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
...
@@ -88,7 +84,6 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
// TODO: if more info is needed, put them in a bundle
// TODO: if more info is needed, put them in a bundle
val
isFirstIssue
=
Vec
(
params
.
numSelect
,
Output
(
Bool
()))
val
isFirstIssue
=
Vec
(
params
.
numSelect
,
Output
(
Bool
()))
val
allSrcReady
=
Vec
(
params
.
numSelect
,
Output
(
Bool
()))
val
allSrcReady
=
Vec
(
params
.
numSelect
,
Output
(
Bool
()))
val
updateMidState
=
Input
(
UInt
(
params
.
numEntries
.
W
))
val
deqRespWidth
=
if
(
params
.
hasFeedback
)
params
.
numDeq
*
2
else
params
.
numDeq
+
params
.
numDeq
+
1
val
deqRespWidth
=
if
(
params
.
hasFeedback
)
params
.
numDeq
*
2
else
params
.
numDeq
+
params
.
numDeq
+
1
val
deqResp
=
Vec
(
deqRespWidth
,
Flipped
(
ValidIO
(
new
Bundle
{
val
deqResp
=
Vec
(
deqRespWidth
,
Flipped
(
ValidIO
(
new
Bundle
{
val
rsMask
=
UInt
(
params
.
numEntries
.
W
)
val
rsMask
=
UInt
(
params
.
numEntries
.
W
)
...
@@ -225,9 +220,6 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
...
@@ -225,9 +220,6 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
case
((
current
,
update
),
wakeup
)
=>
wakeup
||
Mux
(
updateValid
(
i
),
update
,
current
)
case
((
current
,
update
),
wakeup
)
=>
wakeup
||
Mux
(
updateValid
(
i
),
update
,
current
)
})
})
// midState: reset when enqueue; set when receiving feedback
statusNext
.
midState
:=
!
updateValid
(
i
)
&&
(
io
.
updateMidState
(
i
)
||
status
.
midState
)
// static data fields (only updated when instructions enqueue)
// static data fields (only updated when instructions enqueue)
statusNext
.
psrc
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
psrc
,
status
.
psrc
)
statusNext
.
psrc
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
psrc
,
status
.
psrc
)
statusNext
.
srcType
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
srcType
,
status
.
srcType
)
statusNext
.
srcType
:=
Mux
(
updateValid
(
i
),
updateVal
(
i
).
srcType
,
status
.
srcType
)
...
...
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