LoadMissQueue|StoreMissQueue|AtomicsMissQueue|MissQueue:

to avoid output unnecessary logs, only dump state machine state when
state machine are actually working.

src/main/scala/xiangshan/cache/atomicsMissQueue.scala

@@ -42,7 +42,10 @@ class AtomicsMissQueue extends DCacheModule
   io.miss_finish.bits  := DontCare
 
 
+  when (state =/= s_invalid) {
     XSDebug("state: %d\n", state)
+  }
+
   // --------------------------------------------
   // s_invalid: receive requests
   when (state === s_invalid) {

src/main/scala/xiangshan/cache/loadMissQueue.scala

@@ -54,7 +54,10 @@ class LoadMissEntry extends DCacheModule
   io.tag.bits := req_tag
 
 
+  when (state =/= s_invalid) {
     XSDebug("entry: %d state: %d\n", io.id, state)
+  }
+
   // --------------------------------------------
   // s_invalid: receive requests
   when (state === s_invalid) {
@@ -241,8 +244,8 @@ class LoadMissQueue extends DCacheModule
     miss_req.bits.cmd, miss_req.bits.addr, miss_req.bits.client_id)
 
   val miss_resp = io.miss_resp
-  XSDebug(miss_resp.fire(), "miss_resp client_id: %d entry_id: %d\n",
-    miss_resp.bits.client_id, miss_resp.bits.entry_id)
+  XSDebug(miss_resp.fire(), "miss_resp client_id: %d entry_id: %d has_data: %b data: %x\n",
+    miss_resp.bits.client_id, miss_resp.bits.entry_id, miss_resp.bits.has_data, miss_resp.bits.data)
 
   val miss_finish = io.miss_finish
   XSDebug(miss_finish.fire(), "miss_finish client_id: %d entry_id: %d\n",

src/main/scala/xiangshan/cache/missQueue.scala

@@ -141,11 +141,14 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
   io.wb_req.valid        := false.B
   io.wb_req.bits         := DontCare
 
+  when (state =/= s_invalid) {
     XSDebug("entry: %d state: %d\n", io.id, state)
     XSDebug("entry: %d block_idx_valid: %b block_idx: %x block_addr_valid: %b block_addr: %x\n",
       io.id, io.block_idx.valid, io.block_idx.bits, io.block_addr.valid, io.block_addr.bits)
     XSDebug("entry: %d block_probe_idx_valid: %b block_probe_idx: %x block_probe_addr_valid: %b block_probe_addr: %x\n",
       io.id, io.block_probe_idx.valid, io.block_probe_idx.bits, io.block_probe_addr.valid, io.block_probe_addr.bits)
+  }
+
 
   // --------------------------------------------
   // s_invalid: receive requests

src/main/scala/xiangshan/cache/storeMissQueue.scala

@@ -53,7 +53,10 @@ class StoreMissEntry extends DCacheModule
   io.tag.bits := req_tag
 
 
+  when (state =/= s_invalid) {
     XSDebug("entry: %d state: %d\n", io.id, state)
+  }
+
   // --------------------------------------------
   // s_invalid: receive requests
   when (state === s_invalid) {