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8a210a99
编写于
10月 19, 2020
作者:
W
William Wang
浏览文件
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电子邮件补丁
差异文件
[WIP] Lq: parameterize load queue
上级
5b37201d
变更
1
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1 changed file
with
86 addition
and
86 deletion
+86
-86
src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
...ain/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
+86
-86
未找到文件。
src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala
浏览文件 @
8a210a99
...
...
@@ -13,7 +13,7 @@ import xiangshan.mem._
class
LoadQueue
extends
XSModule
with
HasDCacheParameters
with
NeedImpl
{
val
io
=
IO
(
new
Bundle
()
{
val
dp1Req
=
Vec
(
RenameWidth
,
Flipped
(
DecoupledIO
(
new
MicroOp
)))
val
lqIdxs
=
Output
(
Vec
(
RenameWidth
,
UInt
(
L
sroqIdxWidth
.
W
)))
val
lqIdxs
=
Output
(
Vec
(
RenameWidth
,
UInt
(
L
oadQueueIdxWidth
.
W
)))
// LSIdx will be assembled in LSQWrapper
val
brqRedirect
=
Input
(
Valid
(
new
Redirect
))
val
loadIn
=
Vec
(
LoadPipelineWidth
,
Flipped
(
Valid
(
new
LsPipelineBundle
)))
val
storeIn
=
Vec
(
StorePipelineWidth
,
Flipped
(
Valid
(
new
LsPipelineBundle
)))
// FIXME: Valid() only
...
...
@@ -27,30 +27,30 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
// val refill = Flipped(Valid(new DCacheLineReq ))
})
val
uop
=
Reg
(
Vec
(
L
sroq
Size
,
new
MicroOp
))
val
data
=
Reg
(
Vec
(
L
sroqSize
,
new
LsRoqEntry
))
val
allocated
=
RegInit
(
VecInit
(
List
.
fill
(
L
sroqSize
)(
false
.
B
)))
// lsro
q entry has been allocated
val
valid
=
RegInit
(
VecInit
(
List
.
fill
(
L
sroq
Size
)(
false
.
B
)))
// data is valid
val
writebacked
=
RegInit
(
VecInit
(
List
.
fill
(
L
sroq
Size
)(
false
.
B
)))
// inst has been writebacked to CDB
val
commited
=
Reg
(
Vec
(
L
sroq
Size
,
Bool
()))
// inst has been writebacked to CDB
val
miss
=
Reg
(
Vec
(
L
sroq
Size
,
Bool
()))
// load inst missed, waiting for miss queue to accept miss request
val
listening
=
Reg
(
Vec
(
L
sroq
Size
,
Bool
()))
// waiting for refill result
val
pending
=
Reg
(
Vec
(
L
sroq
Size
,
Bool
()))
// mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq
val
ringBufferHeadExtended
=
RegInit
(
0.
U
(
L
sroq
IdxWidth
.
W
))
val
ringBufferTailExtended
=
RegInit
(
0.
U
(
L
sroq
IdxWidth
.
W
))
val
ringBufferHead
=
ringBufferHeadExtended
(
InnerL
sroq
IdxWidth
-
1
,
0
)
val
ringBufferTail
=
ringBufferTailExtended
(
InnerL
sroq
IdxWidth
-
1
,
0
)
val
ringBufferSameFlag
=
ringBufferHeadExtended
(
InnerL
sroqIdxWidth
)
===
ringBufferTailExtended
(
InnerLsroq
IdxWidth
)
val
uop
=
Reg
(
Vec
(
L
oadQueue
Size
,
new
MicroOp
))
val
data
=
Reg
(
Vec
(
L
oadQueueSize
,
new
LsRoqEntry
))
// FIXME: use LoadQueueEntry instead
val
allocated
=
RegInit
(
VecInit
(
List
.
fill
(
L
oadQueueSize
)(
false
.
B
)))
// l
q entry has been allocated
val
valid
=
RegInit
(
VecInit
(
List
.
fill
(
L
oadQueue
Size
)(
false
.
B
)))
// data is valid
val
writebacked
=
RegInit
(
VecInit
(
List
.
fill
(
L
oadQueue
Size
)(
false
.
B
)))
// inst has been writebacked to CDB
val
commited
=
Reg
(
Vec
(
L
oadQueue
Size
,
Bool
()))
// inst has been writebacked to CDB
val
miss
=
Reg
(
Vec
(
L
oadQueue
Size
,
Bool
()))
// load inst missed, waiting for miss queue to accept miss request
val
listening
=
Reg
(
Vec
(
L
oadQueue
Size
,
Bool
()))
// waiting for refill result
val
pending
=
Reg
(
Vec
(
L
oadQueue
Size
,
Bool
()))
// mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of roq
val
ringBufferHeadExtended
=
RegInit
(
0.
U
(
L
oadQueue
IdxWidth
.
W
))
val
ringBufferTailExtended
=
RegInit
(
0.
U
(
L
oadQueue
IdxWidth
.
W
))
val
ringBufferHead
=
ringBufferHeadExtended
(
InnerL
oadQueue
IdxWidth
-
1
,
0
)
val
ringBufferTail
=
ringBufferTailExtended
(
InnerL
oadQueue
IdxWidth
-
1
,
0
)
val
ringBufferSameFlag
=
ringBufferHeadExtended
(
InnerL
oadQueueIdxWidth
)
===
ringBufferTailExtended
(
InnerLoadQueue
IdxWidth
)
val
ringBufferEmpty
=
ringBufferHead
===
ringBufferTail
&&
ringBufferSameFlag
val
ringBufferFull
=
ringBufferHead
===
ringBufferTail
&&
!
ringBufferSameFlag
val
ringBufferAllowin
=
!
ringBufferFull
val
loadCommit
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
(
i
).
valid
&&
!
io
.
commits
(
i
).
bits
.
isWalk
&&
io
.
commits
(
i
).
bits
.
uop
.
ctrl
.
commitType
===
CommitType
.
LOAD
)
val
mcommitIdx
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
(
i
).
bits
.
uop
.
l
sroqIdx
(
InnerLsroq
IdxWidth
-
1
,
0
))
val
mcommitIdx
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
(
i
).
bits
.
uop
.
l
qIdx
(
InnerLoadQueue
IdxWidth
-
1
,
0
))
val
tailMask
=
(((
1.
U
((
L
sroqSize
+
1
).
W
))
<<
ringBufferTail
).
asUInt
-
1.
U
)(
Lsroq
Size
-
1
,
0
)
val
headMask
=
(((
1.
U
((
L
sroqSize
+
1
).
W
))
<<
ringBufferHead
).
asUInt
-
1.
U
)(
Lsroq
Size
-
1
,
0
)
val
tailMask
=
(((
1.
U
((
L
oadQueueSize
+
1
).
W
))
<<
ringBufferTail
).
asUInt
-
1.
U
)(
LoadQueue
Size
-
1
,
0
)
val
headMask
=
(((
1.
U
((
L
oadQueueSize
+
1
).
W
))
<<
ringBufferHead
).
asUInt
-
1.
U
)(
LoadQueue
Size
-
1
,
0
)
val
enqDeqMask1
=
tailMask
^
headMask
val
enqDeqMask
=
Mux
(
ringBufferSameFlag
,
enqDeqMask1
,
~
enqDeqMask1
)
...
...
@@ -61,8 +61,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
XSDebug
(
"(ready, valid): "
)
for
(
i
<-
0
until
RenameWidth
)
{
val
offset
=
if
(
i
==
0
)
0.
U
else
PopCount
(
validDispatch
(
i
-
1
,
0
))
val
l
sro
qIdx
=
ringBufferHeadExtended
+
offset
val
index
=
l
sroqIdx
(
InnerLsroq
IdxWidth
-
1
,
0
)
val
lqIdx
=
ringBufferHeadExtended
+
offset
val
index
=
l
qIdx
(
InnerLoadQueue
IdxWidth
-
1
,
0
)
when
(
io
.
dp1Req
(
i
).
fire
())
{
uop
(
index
)
:=
io
.
dp1Req
(
i
).
bits
allocated
(
index
)
:=
true
.
B
...
...
@@ -79,7 +79,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
}
else
{
io
.
dp1Req
(
i
).
ready
:=
ringBufferAllowin
&&
!
allocated
(
index
)
&&
io
.
dp1Req
(
i
-
1
).
ready
}
io
.
l
sroqIdxs
(
i
)
:=
lsro
qIdx
io
.
l
qIdxs
(
i
)
:=
l
qIdx
XSDebug
(
false
,
true
.
B
,
"(%d, %d) "
,
io
.
dp1Req
(
i
).
ready
,
io
.
dp1Req
(
i
).
valid
)
}
XSDebug
(
false
,
true
.
B
,
"\n"
)
...
...
@@ -87,15 +87,15 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
val
firedDispatch
=
VecInit
((
0
until
CommitWidth
).
map
(
io
.
dp1Req
(
_
).
fire
())).
asUInt
when
(
firedDispatch
.
orR
)
{
ringBufferHeadExtended
:=
ringBufferHeadExtended
+
PopCount
(
firedDispatch
)
XSInfo
(
"dispatched %d insts to l
sro
q\n"
,
PopCount
(
firedDispatch
))
XSInfo
(
"dispatched %d insts to lq\n"
,
PopCount
(
firedDispatch
))
}
// writeback load
(
0
until
LoadPipelineWidth
).
map
(
i
=>
{
when
(
io
.
loadIn
(
i
).
fire
())
{
when
(
io
.
loadIn
(
i
).
bits
.
miss
)
{
XSInfo
(
io
.
loadIn
(
i
).
valid
,
"load miss write to l
sro
q idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n"
,
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
,
XSInfo
(
io
.
loadIn
(
i
).
valid
,
"load miss write to lq idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n"
,
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
,
io
.
loadIn
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
loadIn
(
i
).
bits
.
vaddr
,
io
.
loadIn
(
i
).
bits
.
paddr
,
...
...
@@ -109,7 +109,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
)
}.
otherwise
{
XSInfo
(
io
.
loadIn
(
i
).
valid
,
"load hit write to cbd idx %d pc 0x%x vaddr %x paddr %x data %x mask %x forwardData %x forwardMask: %x mmio %x roll %x exc %x\n"
,
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
,
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
,
io
.
loadIn
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
loadIn
(
i
).
bits
.
vaddr
,
io
.
loadIn
(
i
).
bits
.
paddr
,
...
...
@@ -122,22 +122,22 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
io
.
loadIn
(
i
).
bits
.
uop
.
cf
.
exceptionVec
.
asUInt
)
}
valid
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
!
io
.
loadIn
(
i
).
bits
.
miss
&&
!
io
.
loadIn
(
i
).
bits
.
mmio
writebacked
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
!
io
.
loadIn
(
i
).
bits
.
miss
&&
!
io
.
loadIn
(
i
).
bits
.
mmio
// allocated(io.loadIn(i).bits.uop.l
sroqIdx) := io.loadIn(i).bits.miss // if hit, lsro
q entry can be recycled
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
paddr
:=
io
.
loadIn
(
i
).
bits
.
paddr
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
vaddr
:=
io
.
loadIn
(
i
).
bits
.
vaddr
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
mask
:=
io
.
loadIn
(
i
).
bits
.
mask
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
data
:=
io
.
loadIn
(
i
).
bits
.
data
// for mmio / misc / debug
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
mmio
:=
io
.
loadIn
(
i
).
bits
.
mmio
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
fwdMask
:=
io
.
loadIn
(
i
).
bits
.
forwardMask
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
fwdData
:=
io
.
loadIn
(
i
).
bits
.
forwardData
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
).
exception
:=
io
.
loadIn
(
i
).
bits
.
uop
.
cf
.
exceptionVec
.
asUInt
valid
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
!
io
.
loadIn
(
i
).
bits
.
miss
&&
!
io
.
loadIn
(
i
).
bits
.
mmio
writebacked
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
!
io
.
loadIn
(
i
).
bits
.
miss
&&
!
io
.
loadIn
(
i
).
bits
.
mmio
// allocated(io.loadIn(i).bits.uop.l
qIdx) := io.loadIn(i).bits.miss // if hit, l
q entry can be recycled
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
paddr
:=
io
.
loadIn
(
i
).
bits
.
paddr
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
vaddr
:=
io
.
loadIn
(
i
).
bits
.
vaddr
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
mask
:=
io
.
loadIn
(
i
).
bits
.
mask
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
data
:=
io
.
loadIn
(
i
).
bits
.
data
// for mmio / misc / debug
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
mmio
:=
io
.
loadIn
(
i
).
bits
.
mmio
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
fwdMask
:=
io
.
loadIn
(
i
).
bits
.
forwardMask
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
fwdData
:=
io
.
loadIn
(
i
).
bits
.
forwardData
data
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
).
exception
:=
io
.
loadIn
(
i
).
bits
.
uop
.
cf
.
exceptionVec
.
asUInt
val
dcacheMissed
=
io
.
loadIn
(
i
).
bits
.
miss
&&
!
io
.
loadIn
(
i
).
bits
.
mmio
miss
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
dcacheMissed
listening
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
dcacheMissed
store
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
false
.
B
pending
(
io
.
loadIn
(
i
).
bits
.
uop
.
l
sro
qIdx
)
:=
io
.
loadIn
(
i
).
bits
.
mmio
miss
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
dcacheMissed
listening
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
dcacheMissed
store
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
false
.
B
pending
(
io
.
loadIn
(
i
).
bits
.
uop
.
lqIdx
)
:=
io
.
loadIn
(
i
).
bits
.
mmio
}
})
...
...
@@ -147,7 +147,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
val
reqBlockIndex
=
PriorityEncoder
(~
VecInit
(
inflightReqs
.
map
(
req
=>
req
.
valid
)).
asUInt
)
val
missRefillSelVec
=
VecInit
(
(
0
until
L
sroq
Size
).
map
{
i
=>
(
0
until
L
oadQueue
Size
).
map
{
i
=>
val
inflight
=
inflightReqs
.
map
(
req
=>
req
.
valid
&&
req
.
block_addr
===
get_block_addr
(
data
(
i
).
paddr
)).
reduce
(
_
||
_
)
allocated
(
i
)
&&
miss
(
i
)
&&
!
inflight
})
...
...
@@ -195,11 +195,11 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
when
(
io
.
dcache
.
req
.
fire
()){
XSDebug
(
"miss req: pc:0x%x roqIdx:%d l
sroqIdx:%d (p)addr:0x%x vaddr:0x%x\n"
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
cf
.
pc
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
roqIdx
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
lsro
qIdx
,
io
.
dcache
.
req
.
bits
.
addr
,
io
.
dcache
.
req
.
bits
.
meta
.
vaddr
)
XSDebug
(
"miss req: pc:0x%x roqIdx:%d l
qIdx:%d (p)addr:0x%x vaddr:0x%x\n"
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
cf
.
pc
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
roqIdx
,
io
.
dcache
.
req
.
bits
.
meta
.
uop
.
l
qIdx
,
io
.
dcache
.
req
.
bits
.
addr
,
io
.
dcache
.
req
.
bits
.
meta
.
vaddr
)
}
when
(
io
.
dcache
.
resp
.
fire
()){
XSDebug
(
"miss resp: pc:0x%x roqIdx:%d l
sroqIdx:%d (p)addr:0x%x data %x\n"
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
cf
.
pc
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
roqIdx
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
lsro
qIdx
,
io
.
dcache
.
resp
.
bits
.
meta
.
paddr
,
io
.
dcache
.
resp
.
bits
.
data
)
XSDebug
(
"miss resp: pc:0x%x roqIdx:%d l
qIdx:%d (p)addr:0x%x data %x\n"
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
cf
.
pc
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
roqIdx
,
io
.
dcache
.
resp
.
bits
.
meta
.
uop
.
l
qIdx
,
io
.
dcache
.
resp
.
bits
.
meta
.
paddr
,
io
.
dcache
.
resp
.
bits
.
data
)
}
// Refill 64 bit in a cycle
...
...
@@ -212,7 +212,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
res
.
asUInt
}
(
0
until
L
sroq
Size
).
map
(
i
=>
{
(
0
until
L
oadQueue
Size
).
map
(
i
=>
{
val
blockMatch
=
get_block_addr
(
data
(
i
).
paddr
)
===
io
.
dcache
.
resp
.
bits
.
meta
.
paddr
when
(
allocated
(
i
)
&&
listening
(
i
)
&&
blockMatch
&&
io
.
dcache
.
resp
.
fire
())
{
// split them into words
...
...
@@ -230,10 +230,10 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
// writeback up to 2 missed load insts to CDB
// just randomly pick 2 missed load (data refilled), write them back to cdb
val
loadWbSelVec
=
VecInit
((
0
until
L
sroq
Size
).
map
(
i
=>
{
val
loadWbSelVec
=
VecInit
((
0
until
L
oadQueue
Size
).
map
(
i
=>
{
allocated
(
i
)
&&
valid
(
i
)
&&
!
writebacked
(
i
)
&&
!
store
(
i
)
})).
asUInt
()
// use uint instead vec to reduce verilog lines
val
loadWbSel
=
Wire
(
Vec
(
StorePipelineWidth
,
UInt
(
log2Up
(
L
sroq
Size
).
W
)))
val
loadWbSel
=
Wire
(
Vec
(
StorePipelineWidth
,
UInt
(
log2Up
(
L
oadQueue
Size
).
W
)))
val
lselvec0
=
PriorityEncoderOH
(
loadWbSelVec
)
val
lselvec1
=
PriorityEncoderOH
(
loadWbSelVec
&
(~
lselvec0
).
asUInt
)
loadWbSel
(
0
)
:=
OHToUInt
(
lselvec0
)
...
...
@@ -264,7 +264,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
))
io
.
ldout
(
i
).
bits
.
uop
:=
uop
(
loadWbSel
(
i
))
io
.
ldout
(
i
).
bits
.
uop
.
cf
.
exceptionVec
:=
data
(
loadWbSel
(
i
)).
exception
.
asBools
io
.
ldout
(
i
).
bits
.
uop
.
l
sro
qIdx
:=
loadWbSel
(
i
)
io
.
ldout
(
i
).
bits
.
uop
.
lqIdx
:=
loadWbSel
(
i
)
io
.
ldout
(
i
).
bits
.
data
:=
rdataPartialLoad
io
.
ldout
(
i
).
bits
.
redirectValid
:=
false
.
B
io
.
ldout
(
i
).
bits
.
redirect
:=
DontCare
...
...
@@ -274,7 +274,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
when
(
io
.
ldout
(
i
).
fire
())
{
writebacked
(
loadWbSel
(
i
))
:=
true
.
B
XSInfo
(
io
.
loadIn
(
i
).
valid
,
"load miss write to cbd idx %d pc 0x%x paddr %x data %x mmio %x\n"
,
io
.
ldout
(
i
).
bits
.
uop
.
l
sro
qIdx
,
io
.
ldout
(
i
).
bits
.
uop
.
lqIdx
,
io
.
ldout
(
i
).
bits
.
uop
.
cf
.
pc
,
data
(
loadWbSel
(
i
)).
paddr
,
data
(
loadWbSel
(
i
)).
data
,
...
...
@@ -285,9 +285,9 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
// move tailPtr
// allocatedMask: dequeuePtr can go to the next 1-bit
val
allocatedMask
=
VecInit
((
0
until
L
sroq
Size
).
map
(
i
=>
allocated
(
i
)
||
!
enqDeqMask
(
i
)))
val
allocatedMask
=
VecInit
((
0
until
L
oadQueue
Size
).
map
(
i
=>
allocated
(
i
)
||
!
enqDeqMask
(
i
)))
// find the first one from deqPtr (ringBufferTail)
val
nextTail1
=
getFirstOneWithFlag
(
allocatedMask
,
tailMask
,
ringBufferTailExtended
(
InnerL
sroq
IdxWidth
))
val
nextTail1
=
getFirstOneWithFlag
(
allocatedMask
,
tailMask
,
ringBufferTailExtended
(
InnerL
oadQueue
IdxWidth
))
val
nextTail
=
Mux
(
Cat
(
allocatedMask
).
orR
,
nextTail1
,
ringBufferHeadExtended
)
ringBufferTailExtended
:=
nextTail
...
...
@@ -300,30 +300,30 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
})
// load forward query
// check over all l
sro
q entries and forward data from the first matched store
// check over all lq entries and forward data from the first matched store
// TODO: FIXME
(
0
until
LoadPipelineWidth
).
map
(
i
=>
{
io
.
forward
(
i
).
forwardMask
:=
0.
U
(
8.
W
).
asBools
io
.
forward
(
i
).
forwardData
:=
DontCare
// Compare ringBufferTail (deqPtr) and forward.l
sro
qIdx, we have two cases:
// (1) if they have the same flag, we need to check range(tail, l
sro
qIdx)
// (2) if they have different flags, we need to check range(tail,
lsroqSize) and range(0, lsro
qIdx)
// Forward1: Mux(same_flag, range(tail, l
sroqIdx), range(tail, lsroq
Size))
// Forward2: Mux(same_flag, 0.U, range(0, l
sro
qIdx) )
// Compare ringBufferTail (deqPtr) and forward.lqIdx, we have two cases:
// (1) if they have the same flag, we need to check range(tail, lqIdx)
// (2) if they have different flags, we need to check range(tail,
LoadQueueSize) and range(0, l
qIdx)
// Forward1: Mux(same_flag, range(tail, l
qIdx), range(tail, LoadQueue
Size))
// Forward2: Mux(same_flag, 0.U, range(0, lqIdx) )
// i.e. forward1 is the target entries with the same flag bits and forward2 otherwise
val
forwardMask1
=
WireInit
(
VecInit
(
Seq
.
fill
(
8
)(
false
.
B
)))
val
forwardData1
=
WireInit
(
VecInit
(
Seq
.
fill
(
8
)(
0.
U
(
8.
W
))))
val
forwardMask2
=
WireInit
(
VecInit
(
Seq
.
fill
(
8
)(
false
.
B
)))
val
forwardData2
=
WireInit
(
VecInit
(
Seq
.
fill
(
8
)(
0.
U
(
8.
W
))))
val
differentFlag
=
ringBufferTailExtended
(
InnerL
sroqIdxWidth
)
=/=
io
.
forward
(
i
).
lsroqIdx
(
InnerLsroq
IdxWidth
)
val
forwardMask
=
((
1.
U
((
L
sroqSize
+
1
).
W
))
<<
io
.
forward
(
i
).
lsroqIdx
(
InnerLsroq
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
differentFlag
=
ringBufferTailExtended
(
InnerL
oadQueueIdxWidth
)
=/=
io
.
forward
(
i
).
lqIdx
(
InnerLoadQueue
IdxWidth
)
val
forwardMask
=
((
1.
U
((
L
oadQueueSize
+
1
).
W
))
<<
io
.
forward
(
i
).
lqIdx
(
InnerLoadQueue
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
needForward1
=
Mux
(
differentFlag
,
~
tailMask
,
tailMask
^
forwardMask
)
val
needForward2
=
Mux
(
differentFlag
,
forwardMask
,
0.
U
(
L
sroq
Size
.
W
))
val
needForward2
=
Mux
(
differentFlag
,
forwardMask
,
0.
U
(
L
oadQueue
Size
.
W
))
// entry with larger index should have higher priority since it's data is younger
for
(
j
<-
0
until
L
sroq
Size
)
{
for
(
j
<-
0
until
L
oadQueue
Size
)
{
val
needCheck
=
valid
(
j
)
&&
allocated
(
j
)
&&
// all valid terms need to be checked
io
.
forward
(
i
).
paddr
(
PAddrBits
-
1
,
3
)
===
data
(
j
).
paddr
(
PAddrBits
-
1
,
3
)
(
0
until
XLEN
/
8
).
foreach
(
k
=>
{
...
...
@@ -391,10 +391,10 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
}
def
rangeMask
(
start
:
UInt
,
end
:
UInt
)
:
UInt
=
{
val
startMask
=
(
1.
U
((
L
sroqSize
+
1
).
W
)
<<
start
(
InnerLsroq
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
endMask
=
(
1.
U
((
L
sroqSize
+
1
).
W
)
<<
end
(
InnerLsroq
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
xorMask
=
startMask
(
L
sroqSize
-
1
,
0
)
^
endMask
(
Lsroq
Size
-
1
,
0
)
Mux
(
start
(
InnerL
sroqIdxWidth
)
===
end
(
InnerLsroq
IdxWidth
),
xorMask
,
~
xorMask
)
val
startMask
=
(
1.
U
((
L
oadQueueSize
+
1
).
W
)
<<
start
(
InnerLoadQueue
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
endMask
=
(
1.
U
((
L
oadQueueSize
+
1
).
W
)
<<
end
(
InnerLoadQueue
IdxWidth
-
1
,
0
)).
asUInt
-
1.
U
val
xorMask
=
startMask
(
L
oadQueueSize
-
1
,
0
)
^
endMask
(
LoadQueue
Size
-
1
,
0
)
Mux
(
start
(
InnerL
oadQueueIdxWidth
)
===
end
(
InnerLoadQueue
IdxWidth
),
xorMask
,
~
xorMask
)
}
// store backward query and rollback
...
...
@@ -403,12 +403,12 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
rollback
(
i
)
:=
DontCare
when
(
io
.
storeIn
(
i
).
valid
)
{
val
startIndex
=
io
.
storeIn
(
i
).
bits
.
uop
.
l
sroqIdx
(
InnerLsroq
IdxWidth
-
1
,
0
)
val
l
sroqIdxMask
=
((
1.
U
((
LsroqSize
+
1
).
W
)
<<
startIndex
).
asUInt
-
1.
U
)(
Lsroq
Size
-
1
,
0
)
val
xorMask
=
l
sro
qIdxMask
^
headMask
val
sameFlag
=
io
.
storeIn
(
i
).
bits
.
uop
.
l
sroqIdx
(
InnerLsroqIdxWidth
)
===
ringBufferHeadExtended
(
InnerLsroq
IdxWidth
)
val
startIndex
=
io
.
storeIn
(
i
).
bits
.
uop
.
l
qIdx
(
InnerLoadQueue
IdxWidth
-
1
,
0
)
val
l
qIdxMask
=
((
1.
U
((
LoadQueueSize
+
1
).
W
)
<<
startIndex
).
asUInt
-
1.
U
)(
LoadQueue
Size
-
1
,
0
)
val
xorMask
=
lqIdxMask
^
headMask
val
sameFlag
=
io
.
storeIn
(
i
).
bits
.
uop
.
l
qIdx
(
InnerLoadQueueIdxWidth
)
===
ringBufferHeadExtended
(
InnerLoadQueue
IdxWidth
)
val
toEnqPtrMask
=
Mux
(
sameFlag
,
xorMask
,
~
xorMask
)
val
l
sroqViolationVec
=
VecInit
((
0
until
Lsroq
Size
).
map
(
j
=>
{
val
l
qViolationVec
=
VecInit
((
0
until
LoadQueue
Size
).
map
(
j
=>
{
val
addrMatch
=
allocated
(
j
)
&&
io
.
storeIn
(
i
).
bits
.
paddr
(
PAddrBits
-
1
,
3
)
===
data
(
j
).
paddr
(
PAddrBits
-
1
,
3
)
val
entryNeedCheck
=
toEnqPtrMask
(
j
)
&&
addrMatch
&&
(
valid
(
j
)
||
listening
(
j
)
||
miss
(
j
))
...
...
@@ -416,10 +416,10 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
val
violationVec
=
(
0
until
8
).
map
(
k
=>
data
(
j
).
mask
(
k
)
&&
io
.
storeIn
(
i
).
bits
.
mask
(
k
))
Cat
(
violationVec
).
orR
()
&&
entryNeedCheck
}))
val
l
sroqViolation
=
lsro
qViolationVec
.
asUInt
().
orR
()
val
l
sroqViolationIndex
=
getFirstOne
(
lsroqViolationVec
,
lsro
qIdxMask
)
val
l
sroqViolationUop
=
uop
(
lsro
qViolationIndex
)
XSDebug
(
l
sroqViolation
,
p
"${Binary(Cat(lsroqViolationVec))}, $startIndex, $lsro
qViolationIndex\n"
)
val
l
qViolation
=
l
qViolationVec
.
asUInt
().
orR
()
val
l
qViolationIndex
=
getFirstOne
(
lqViolationVec
,
l
qIdxMask
)
val
l
qViolationUop
=
uop
(
l
qViolationIndex
)
XSDebug
(
l
qViolation
,
p
"${Binary(Cat(lqViolationVec))}, $startIndex, $l
qViolationIndex\n"
)
// when l/s writeback to roq together, check if rollback is needed
val
wbViolationVec
=
VecInit
((
0
until
LoadPipelineWidth
).
map
(
j
=>
{
...
...
@@ -442,8 +442,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
val
l4Violation
=
l4ViolationVec
.
asUInt
().
orR
()
val
l4ViolationUop
=
getOldestInTwo
(
l4ViolationVec
,
io
.
forward
.
map
(
_
.
uop
))
val
rollbackValidVec
=
Seq
(
l
sro
qViolation
,
wbViolation
,
l4Violation
)
val
rollbackUopVec
=
Seq
(
l
sro
qViolationUop
,
wbViolationUop
,
l4ViolationUop
)
val
rollbackValidVec
=
Seq
(
lqViolation
,
wbViolation
,
l4Violation
)
val
rollbackUopVec
=
Seq
(
lqViolationUop
,
wbViolationUop
,
l4ViolationUop
)
rollback
(
i
).
valid
:=
Cat
(
rollbackValidVec
).
orR
val
mask
=
getAfterMask
(
rollbackValidVec
,
rollbackUopVec
)
val
oneAfterZero
=
mask
(
1
)(
0
)
...
...
@@ -458,9 +458,9 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
rollback
(
i
).
bits
.
isFlushPipe
:=
false
.
B
XSDebug
(
l
sro
qViolation
,
lqViolation
,
"need rollback (ld wb before store) pc %x roqidx %d target %x\n"
,
io
.
storeIn
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
storeIn
(
i
).
bits
.
uop
.
roqIdx
,
l
sro
qViolationUop
.
roqIdx
io
.
storeIn
(
i
).
bits
.
uop
.
cf
.
pc
,
io
.
storeIn
(
i
).
bits
.
uop
.
roqIdx
,
lqViolationUop
.
roqIdx
)
XSDebug
(
wbViolation
,
...
...
@@ -494,7 +494,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
// Memory mapped IO / other uncached operations
// setup misc mem access req
// mask / paddr / data can be get from l
sro
q.data
// mask / paddr / data can be get from lq.data
val
commitType
=
io
.
commits
(
0
).
bits
.
uop
.
ctrl
.
commitType
io
.
uncache
.
req
.
valid
:=
pending
(
ringBufferTail
)
&&
allocated
(
ringBufferTail
)
&&
commitType
===
CommitType
.
LOAD
&&
...
...
@@ -544,15 +544,15 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
// FIXME: index by lq/sq id
// Read vaddr for mem exception
val
mexcLs
roqIdx
=
WireInit
(
0.
U
(
LsroqIdxWidth
.
W
))
val
memExceptionAddr
=
WireInit
(
data
(
mexcLs
roqIdx
(
InnerLsroq
IdxWidth
-
1
,
0
)).
vaddr
)
ExcitingUtils
.
addSink
(
mexcLs
roq
Idx
,
"EXECPTION_LSROQIDX"
)
val
mexcLs
Idx
=
WireInit
(
0.
asTypeOf
(
new
LSIdx
()
))
val
memExceptionAddr
=
WireInit
(
data
(
mexcLs
Idx
.
lqIdx
(
InnerLoadQueue
IdxWidth
-
1
,
0
)).
vaddr
)
ExcitingUtils
.
addSink
(
mexcLsIdx
,
"EXECPTION_LSROQIDX"
)
ExcitingUtils
.
addSource
(
memExceptionAddr
,
"EXECPTION_LOAD_VADDR"
)
// misprediction recovery / exception redirect
// invalidate l
sro
q term using robIdx
val
needCancel
=
Wire
(
Vec
(
L
sroq
Size
,
Bool
()))
for
(
i
<-
0
until
L
sroq
Size
)
{
// invalidate lq term using robIdx
val
needCancel
=
Wire
(
Vec
(
L
oadQueue
Size
,
Bool
()))
for
(
i
<-
0
until
L
oadQueue
Size
)
{
needCancel
(
i
)
:=
uop
(
i
).
needFlush
(
io
.
brqRedirect
)
&&
allocated
(
i
)
&&
!
commited
(
i
)
when
(
needCancel
(
i
))
{
when
(
io
.
brqRedirect
.
bits
.
isReplay
){
...
...
@@ -576,7 +576,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
}
// debug info
XSDebug
(
"head %d:%d tail %d:%d scommit %d\n"
,
ringBufferHeadExtended
(
InnerL
sroqIdxWidth
),
ringBufferHead
,
ringBufferTailExtended
(
InnerLsroq
IdxWidth
),
ringBufferTail
,
scommitPending
)
XSDebug
(
"head %d:%d tail %d:%d scommit %d\n"
,
ringBufferHeadExtended
(
InnerL
oadQueueIdxWidth
),
ringBufferHead
,
ringBufferTailExtended
(
InnerLoadQueue
IdxWidth
),
ringBufferTail
,
scommitPending
)
def
PrintFlag
(
flag
:
Bool
,
name
:
String
)
:
Unit
=
{
when
(
flag
)
{
...
...
@@ -586,7 +586,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with NeedImpl {
}
}
for
(
i
<-
0
until
L
sroq
Size
)
{
for
(
i
<-
0
until
L
oadQueue
Size
)
{
if
(
i
%
4
==
0
)
XSDebug
(
""
)
XSDebug
(
false
,
true
.
B
,
"%x "
,
uop
(
i
).
cf
.
pc
)
PrintFlag
(
allocated
(
i
),
"a"
)
...
...
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