// NOTE: just for simple tlb debug, comment it after tlb's debug
for(i<-0untilWidth){
if(isDtlb){
XSDebug(!(!vmEnable||RegNext(req(i).bits.vaddr)===resp(i).bits.paddr||!resp(i).valid||resp(i).bits.miss),p"Dtlb: vaddr:${Hexadecimal(RegNext(req(i).bits.vaddr))} paddr:${Hexadecimal(resp(i).bits.paddr)} should be equal\n")
XSDebug(!(!vmEnable||req(i).bits.vaddr===resp(i).bits.paddr||!resp(i).valid)||resp(i).bits.miss,p"Itlb: vaddr:${Hexadecimal(RegNext(req(i).bits.vaddr))} paddr:${Hexadecimal(resp(i).bits.paddr)} should be equal\n")