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提交 571a2e69 编写于 作者: J jinyue
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IssueQueue:add src3 debug info

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src/main/scala/xiangshan/backend/issue/IssueQueue.scala
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...@@ -185,13 +185,13 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int = ...@@ -185,13 +185,13 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
} }
XSDebug("[Reg info-ENQ] enqSelNext:%d | enqFireNext:%d \n",enqSelNext,enqFireNext) XSDebug("[Reg info-ENQ] enqSelNext:%d | enqFireNext:%d \n",enqSelNext,enqFireNext)
XSDebug("[IQ content] valid vr vf| pc insruction | src1rdy src1 | src2Rdy src2 pdest \n") XSDebug("[IQ content] valid vr vf| pc insruction | src1rdy src1 | src2Rdy src2 | src3Rdy src3| pdest \n")
for(i <- 0 to (iqSize -1)){ for(i <- 0 to (iqSize -1)){
val ins = ctrlFlow(i).instr val ins = ctrlFlow(i).instr
val pc = ctrlFlow(i).pc val pc = ctrlFlow(i).pc
XSDebug(valid(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d valid|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i), pc,ins,src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) XSDebug(valid(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i), pc,ins,src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i))
XSDebug(validReg(i) && validWillFalse(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d valid will be False|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) XSDebug(validReg(i) && validWillFalse(i),"[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d valid will be False|\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i))
XSDebug("[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %d\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),prfDest(i)) XSDebug("[IQ content][%d] %d%d%d |%x %x| %x %x | %x %x | %x %x | %d\n",i.asUInt, valid(i), validReg(i), validWillFalse(i),pc,ins, src1Rdy(i), src1Data(i), src2Rdy(i), src2Data(i),src3Rdy(i), src3Data(i),prfDest(i))
} }
// From Common Data Bus(wakeUpPort) // From Common Data Bus(wakeUpPort)
// chisel claims that firrtl will optimize Mux1H to and/or tree // chisel claims that firrtl will optimize Mux1H to and/or tree
......
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